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| author | Jim Wilson <wilson@tuliptree.org> | 2002-12-05 02:08:02 +0000 |
|---|---|---|
| committer | Jim Wilson <wilson@tuliptree.org> | 2002-12-05 02:08:02 +0000 |
| commit | c10d9d8fc3e815f9cbbf3be2188ddb94e4635ac9 (patch) | |
| tree | 060d0f181868d4dfeac327c4111706a2221bf3fa /opcodes/ia64-opc-f.c | |
| parent | 27e829d0372c529518abf58c384aa80936677a95 (diff) | |
| download | gdb-c10d9d8fc3e815f9cbbf3be2188ddb94e4635ac9.zip gdb-c10d9d8fc3e815f9cbbf3be2188ddb94e4635ac9.tar.gz gdb-c10d9d8fc3e815f9cbbf3be2188ddb94e4635ac9.tar.bz2 | |
Patch to update IA-64 port to SDM 2.1.
bfd/ChangeLog
* cpu-ia64-opc.c: Add operand constant "ar.csd".
gas/ChangeLog
* config/tc-ia64.c (pseudo_func): Add "@pause" constant for "hint"
instruction.
(emit_one_bundle): Handle "hint" instruction.
(operand_match): Match IA64_OPND_AR_CSD.
gas/testsuite/ChangeLog
* gas/ia64/opc-b.d: Update for instructions added by SDM2.1.
* gas/ia64/opc-b.s: Ditto.
* gas/ia64/opc-f.d: Ditto.
* gas/ia64/opc-f.s: Ditto.
* gas/ia64/opc-i.d: Ditto.
* gas/ia64/opc-i.s: Ditto.
* gas/ia64/opc-m.d: Ditto.
* gas/ia64/opc-m.s: Ditto.
* gas/ia64/opc-x.d: Ditto.
* gas/ia64/opc-x.s: Ditto.
include/opcode/ChangeLog
* ia64.h: Fix copyright message.
(IA64_OPND_AR_CSD): New operand kind.
opcodes/ChangeLog
* ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction.
* ia64-opc-b.c: Add "hint.b" instruction.
* ia64-opc-f.c: Add "hint.f" instruction.
* ia64-opc-i.c: Add "hint.i" instruction.
* ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and
"cmp8xchg16" instructions.
* ia64-opc-x.c: Add "hint.x" instruction.
* ia64-opc.h (AR_CSD): New macro.
* ia64-ic.tbl: Update according to SDM2.1.
* ia64-raw.tbl: Ditto.
* ia64-waw.tbl: Ditto.
* ia64-gen.c (in_iclass): Handle "hint" like "nop".
(lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD],
AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR].
* ia64-asmtab.c: Regenerate.
Diffstat (limited to 'opcodes/ia64-opc-f.c')
| -rw-r--r-- | opcodes/ia64-opc-f.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/opcodes/ia64-opc-f.c b/opcodes/ia64-opc-f.c index 41d4a00..89dbcde 100644 --- a/opcodes/ia64-opc-f.c +++ b/opcodes/ia64-opc-f.c @@ -36,6 +36,7 @@ #define bXb(x) (((ia64_insn) ((x) & 0x1)) << 33) #define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) #define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26) #define mF2 bF2 (-1) #define mF4 bF4 (-1) @@ -48,6 +49,7 @@ #define mXb bXb (-1) #define mX2 bX2 (-1) #define mX6 bX6 (-1) +#define mY bY (-1) #define OpXa(a,b) (bOp (a) | bXa (b)), (mOp | mXa) #define OpXaSf(a,b,c) (bOp (a) | bXa (b) | bSf (c)), (mOp | mXa | mSf) @@ -69,6 +71,8 @@ (bOp (a) | bXb (b) | bQ (c) | bSf (d)), (mOp | mXb | mQ | mSf) #define OpXbX6(a,b,c) \ (bOp (a) | bXb (b) | bX6 (c)), (mOp | mXb | mX6) +#define OpXbX6Y(a,b,c,d) \ + (bOp (a) | bXb (b) | bX6 (c) | bY (d)), (mOp | mXb | mX6 | mY) #define OpXbX6F2(a,b,c,d) \ (bOp (a) | bXb (b) | bX6 (c) | bF2 (d)), (mOp | mXb | mX6 | mF2) #define OpXbX6Sf(a,b,c,d) \ @@ -177,7 +181,8 @@ struct ia64_opcode ia64_opcodes_f[] = {"fchkf.s3", f0, OpXbX6Sf (0, 0, 0x08, 3), {TGT25}, EMPTY}, {"break.f", f0, OpXbX6 (0, 0, 0x00), {IMMU21}, EMPTY}, - {"nop.f", f0, OpXbX6 (0, 0, 0x01), {IMMU21}, EMPTY}, + {"nop.f", f0, OpXbX6Y (0, 0, 0x01, 0), {IMMU21}, EMPTY}, + {"hint.f", f0, OpXbX6Y (0, 0, 0x01, 1), {IMMU21}, EMPTY}, {"fprcpa.s0", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, EMPTY}, {"fprcpa", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NULL}, |