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authorH.J. Lu <hjl.tools@gmail.com>2012-08-17 17:12:36 +0000
committerH.J. Lu <hjl.tools@gmail.com>2012-08-17 17:12:36 +0000
commit7b458c12dc33fc7af4c67c138feaa5f034351bac (patch)
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parentee8206a9d3d82b01d3108b83e36491fd6693db4d (diff)
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Add AMD btver1 and btver2 support
gas/ 2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com> * config/tc-i386.c (cpu_arch): Add CPU_BTVER1_FLAGS and CPU_BTVER2_FLAGS. (i386_align_code): Add case for PROCESSOR_BT. * config/tc-i386.h (enum processor_type): Add PROCESSOR_BT. * doc/c-i386.texi: Add -march={btver1, btver2} options. gas/testsuite/ 2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com> * gas/i386/i386.exp: Run btver1 and btver2 test cases. * gas/i386/nops-1-btver1.d: New. * gas/i386/nops-1-btver2.d: New. * gas/i386/arch-10-btver1.d: New. * gas/i386/arch-10-btver2.d: New. * gas/i386/x86-64-nops-1-btver1.d: New. * gas/i386/x86-64-nops-1-btver2.d: New. * gas/i386/x86-64-arch-2-btver1.d: New. * gas/i386/x86-64-arch-2-btver2.d: New. opcodes/ 2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com> * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and CPU_BTVER2_FLAGS. * i386-opc.h: Update CpuPRFCHW comment. * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
Diffstat (limited to 'opcodes/i386-tbl.h')
-rw-r--r--opcodes/i386-tbl.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index faca6bb..001a966 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -38403,7 +38403,7 @@ const insn_template i386_optab[] =
{ "prefetch", 1, 0xf0d, 0x0, 2,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0 } },
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,