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author | H.J. Lu <hjl.tools@gmail.com> | 2007-08-09 13:50:51 +0000 |
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committer | H.J. Lu <hjl.tools@gmail.com> | 2007-08-09 13:50:51 +0000 |
commit | c3ad16c0cde34747ea3f1d3fb9c17dd85d9ca475 (patch) | |
tree | e4b2fdea68189bd7bd08c79dd73a6d975bceb9ac /opcodes/i386-tbl.h | |
parent | 1e1c6a43f8cc11e8d7d3809074d762c5a0a8d62e (diff) | |
download | gdb-c3ad16c0cde34747ea3f1d3fb9c17dd85d9ca475.zip gdb-c3ad16c0cde34747ea3f1d3fb9c17dd85d9ca475.tar.gz gdb-c3ad16c0cde34747ea3f1d3fb9c17dd85d9ca475.tar.bz2 |
gas/
2007-08-09 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (check_byte_reg): Support pextrb and pinsrb.
gas/testsuite/
2007-08-09 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run sse4_1-intel, sse4_2-intel,
x86-64-sse4_1-intel and x86-64-sse4_2-intel.
* gas/i386/sse4_1-intel.d: New file.
* gas/i386/sse4_2-intel.d: Likewise.
* gas/i386/x86-64-sse4_1-intel.d: Likewise.
* gas/i386/x86-64-sse4_2-intel.d: Likewise.
* gas/i386/sse4_1.s: Add tests for Intel syntax.
* gas/i386/sse4_2.s: Likewise.
* gas/i386/x86-64-sse4_1.s: Likewise.
* gas/i386/x86-64-sse4_2.s: Likewise.
* gas/i386/sse4_1.d: Updated.
* gas/i386/sse4_2.d: Likewise.
* gas/i386/x86-64-sse4_1.d: Likewise.
* gas/i386/x86-64-sse4_2.d: Likewise.
opcodes/
2007-08-09 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add NoRex64 to pmovsxbw, pmovsxwd, pmovsxdq,
pmovzxbw, pmovzxwd, pmovzxdq and roundsd.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-tbl.h')
-rw-r--r-- | opcodes/i386-tbl.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index afe848c..d1874d3 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -3947,7 +3947,7 @@ const template i386_optab[] = { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxbw", 2, 0x660f3820, None, CpuSSE4_1, - Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxbd", 2, 0x660f3821, None, CpuSSE4_1, @@ -3959,7 +3959,7 @@ const template i386_optab[] = { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxwd", 2, 0x660f3823, None, CpuSSE4_1, - Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxwq", 2, 0x660f3824, None, CpuSSE4_1, @@ -3967,11 +3967,11 @@ const template i386_optab[] = { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovsxdq", 2, 0x660f3825, None, CpuSSE4_1, - Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxbw", 2, 0x660f3830, None, CpuSSE4_1, - Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxbd", 2, 0x660f3831, None, CpuSSE4_1, @@ -3983,7 +3983,7 @@ const template i386_optab[] = { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxwd", 2, 0x660f3833, None, CpuSSE4_1, - Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxwq", 2, 0x660f3834, None, CpuSSE4_1, @@ -3991,7 +3991,7 @@ const template i386_optab[] = { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmovzxdq", 2, 0x660f3835, None, CpuSSE4_1, - Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "pmuldq", 2, 0x660f3828, None, CpuSSE4_1, @@ -4017,7 +4017,7 @@ const template i386_optab[] = BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, { "roundsd", 3, 0x660f3a0b, None, CpuSSE4_1, - Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, + Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { Imm8, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } }, |