diff options
| author | H.J. Lu <hjl.tools@gmail.com> | 2007-08-31 18:48:29 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2007-08-31 18:48:29 +0000 |
| commit | 144c41d9920221498b4a4f5b9cf504ffe2925957 (patch) | |
| tree | 23b57d0fc35e190169a544d20f7363a95e9fc42f /opcodes/i386-tbl.h | |
| parent | bccc275a135787a5ea86a6492f387dbbe4dd2080 (diff) | |
| download | gdb-144c41d9920221498b4a4f5b9cf504ffe2925957.zip gdb-144c41d9920221498b4a4f5b9cf504ffe2925957.tar.gz gdb-144c41d9920221498b4a4f5b9cf504ffe2925957.tar.bz2 | |
gas/testsuite/
2007-08-31 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/svme.s: Updated to accept eax in 32bit and rax in
64bit.
* gas/i386/svme.d: Updated.
* gas/i386/svme64.d: Likewise.
opcodes/
2007-08-31 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (SVME_Fixup): Removed.
(OPC_EXT_39): New.
(OPC_EXT_RM_6): Likewise.
(grps): Use OPC_EXT_39.
(opc_ext_table): Add OPC_EXT_39.
(opc_ext_rm_table): Add OPC_EXT_RM_6.
* i386-opc.tbl: Correct SVME instructions to take register
operand only.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-tbl.h')
| -rw-r--r-- | opcodes/i386-tbl.h | 31 |
1 files changed, 22 insertions, 9 deletions
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index d1874d3..362ae46 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -4189,40 +4189,53 @@ const template i386_optab[] = { "invlpga", 0, 0xf01, 0xdf, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, - { "invlpga", 2, 0xf01, 0xdf, CpuSVME, + { "invlpga", 2, 0xf01, 0xdf, CpuSVME|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, - { BaseIndex|Disp8|Disp16|Disp32|Disp32S, + { Reg32, + Reg32 } }, + { "invlpga", 2, 0xf01, 0xdf, CpuSVME|Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, + { Reg64, Reg32 } }, { "skinit", 0, 0xf01, 0xde, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "skinit", 1, 0xf01, 0xde, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, - { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { Reg32 } }, { "stgi", 0, 0xf01, 0xdc, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "vmload", 0, 0xf01, 0xda, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, - { "vmload", 1, 0xf01, 0xda, CpuSVME, + { "vmload", 1, 0xf01, 0xda, CpuSVME|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, - { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { Reg32 } }, + { "vmload", 1, 0xf01, 0xda, CpuSVME|Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, + { Reg64 } }, { "vmmcall", 0, 0xf01, 0xd9, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, { "vmrun", 0, 0xf01, 0xd8, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, - { "vmrun", 1, 0xf01, 0xd8, CpuSVME, + { "vmrun", 1, 0xf01, 0xd8, CpuSVME|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, - { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { Reg32 } }, + { "vmrun", 1, 0xf01, 0xd8, CpuSVME|Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, + { Reg64 } }, { "vmsave", 0, 0xf01, 0xdb, CpuSVME, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } }, - { "vmsave", 1, 0xf01, 0xdb, CpuSVME, + { "vmsave", 1, 0xf01, 0xdb, CpuSVME|CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, - { BaseIndex|Disp8|Disp16|Disp32|Disp32S } }, + { Reg32 } }, + { "vmsave", 1, 0xf01, 0xdb, CpuSVME|Cpu64, + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt|NoRex64, + { Reg64 } }, { "movntsd", 2, 0xf20f2b, None, CpuSSE4a, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM, |