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author | Jan Beulich <jbeulich@suse.com> | 2019-07-16 09:30:29 +0200 |
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committer | Jan Beulich <jbeulich@suse.com> | 2019-07-16 09:30:29 +0200 |
commit | 21df382b918888de64749e977f185c4e10a5b838 (patch) | |
tree | 0304ccc5838584e7f3cadb92a206e4a2b616fed8 /opcodes/i386-reg.tbl | |
parent | 206e6c58a769f9ec63827b8ca3952b0cd8c828ba (diff) | |
download | gdb-21df382b918888de64749e977f185c4e10a5b838.zip gdb-21df382b918888de64749e977f185c4e10a5b838.tar.gz gdb-21df382b918888de64749e977f185c4e10a5b838.tar.bz2 |
x86: fold SReg{2,3}
They're the only exception to there generally being no mix of register
kinds possible in an insn operand template, and there being two bits per
operand for their representation is also quite wasteful, considering the
low number of uses. Fold both bits and deal with the little bit of
fallout.
Also take the liberty and drop dead code trying to set REX_B: No segment
register has RegRex set on it.
Additionally I was quite surprised that PUSH/POP with the permitted
segment registers is not covered by the test cases. Add the missing
pieces.
Diffstat (limited to 'opcodes/i386-reg.tbl')
-rw-r--r-- | opcodes/i386-reg.tbl | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index 04c6d15..ba4c51c 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -105,13 +105,13 @@ k5, RegMask, 0, 5, 98, 123 k6, RegMask, 0, 6, 99, 124 k7, RegMask, 0, 7, 100, 125 // Segment registers. -es, SReg2, 0, 0, 40, 50 -cs, SReg2, 0, 1, 41, 51 -ss, SReg2, 0, 2, 42, 52 -ds, SReg2, 0, 3, 43, 53 -fs, SReg3, 0, 4, 44, 54 -gs, SReg3, 0, 5, 45, 55 -flat, SReg3, 0, RegFlat, Dw2Inval, Dw2Inval +es, SReg, 0, 0, 40, 50 +cs, SReg, 0, 1, 41, 51 +ss, SReg, 0, 2, 42, 52 +ds, SReg, 0, 3, 43, 53 +fs, SReg, 0, 4, 44, 54 +gs, SReg, 0, 5, 45, 55 +flat, SReg, 0, RegFlat, Dw2Inval, Dw2Inval // Control registers. cr0, Control, 0, 0, Dw2Inval, Dw2Inval cr1, Control, 0, 1, Dw2Inval, Dw2Inval |