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| author | H.J. Lu <hjl.tools@gmail.com> | 2008-05-21 21:40:57 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2008-05-21 21:40:57 +0000 |
| commit | d9479f2d8d28e7ec51ea26d1780944c8ea40b9f1 (patch) | |
| tree | ea14d3a994be722146e09ea8e4cc07d8fbdab1a2 /opcodes/i386-opc.tbl | |
| parent | 7d9e3d985416edccb274f0c704901839234cf4a9 (diff) | |
| download | gdb-d9479f2d8d28e7ec51ea26d1780944c8ea40b9f1.zip gdb-d9479f2d8d28e7ec51ea26d1780944c8ea40b9f1.tar.gz gdb-d9479f2d8d28e7ec51ea26d1780944c8ea40b9f1.tar.bz2 | |
gas/testsuite/
2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/sse-noavx.s: Add tests for movdq2q and movq2dq.
* gas/i386/x86-64-sse-noavx.s: Likewise.
* gas/i386/sse-noavx.d: Updated.
* gas/i386/x86-64-sse-noavx.d: Likewise.
opcodes/
2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-opc.tbl')
| -rw-r--r-- | opcodes/i386-opc.tbl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 35c0f90..3b8e234 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1453,8 +1453,8 @@ movdqu, 2, 0xf36f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|N movdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } movdqu, 2, 0xf30f6f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movdqu, 2, 0xf30f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } -movdq2q, 2, 0xf20fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegMMX } -movq2dq, 2, 0xf30fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, RegXMM } +movdq2q, 2, 0xf20fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegXMM, RegMMX } +movq2dq, 2, 0xf30fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, RegXMM } pmuludq, 2, 0x66f4, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmuludq, 2, 0x660ff4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmuludq, 2, 0xff4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } |