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authorGanesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>2015-03-17 21:49:15 +0530
committerGanesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>2015-03-17 21:49:15 +0530
commit029f3522619e8b77a7b848be23f4c13e50087d8b (patch)
tree484cbee2753ca7c12d2d0db7a28864e2e45e7456 /opcodes/i386-opc.tbl
parent393bd0c06b64ff6076f28053cbd2fce352023c70 (diff)
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Add znver1 processor
Diffstat (limited to 'opcodes/i386-opc.tbl')
-rw-r--r--opcodes/i386-opc.tbl7
1 files changed, 7 insertions, 0 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 5151000..6edc121 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -5922,3 +5922,10 @@ vpermt2b, 3, 0x667D, None, 1, CpuAVX512VBMI|CpuAVX512VL, Modrm|EVex=2|Masking=3|
vpermt2b, 3, 0x667D, None, 1, CpuAVX512VBMI|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
// AVX512VBMI instructions end
+
+// CLZERO instructions
+
+clzero, 0, 0xf01fc, None, 3, CpuCLZERO, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+
+// CLZERO instructions end
+