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| author | Ilya Tocar <ilya.tocar@intel.com> | 2014-04-03 16:40:04 +0400 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2014-04-04 08:24:47 -0700 |
| commit | 2cf200a4c8a850e6f696e572ea03f340eae97c8a (patch) | |
| tree | 8828a6b643d1568b47b5720a43a41a99dc6695b2 /opcodes/i386-opc.tbl | |
| parent | 26954155a64f1a6a24b96213a8ee2f5390e649c6 (diff) | |
| download | gdb-2cf200a4c8a850e6f696e572ea03f340eae97c8a.zip gdb-2cf200a4c8a850e6f696e572ea03f340eae97c8a.tar.gz gdb-2cf200a4c8a850e6f696e572ea03f340eae97c8a.tar.bz2 | |
Add support for Intel SGX instructions
Add Intel SGX instructions support to assembler and disassembler.
gas/
* config/tc-i386.c (cpu_arch): Add .se1.
* doc/c-i386.texi: Document .se1/se1.
gas/testsuite/
* gas/i386/i386.exp: Run SE1 tests.
* gas/i386/se1.d: New file.
* gas/i386/se1.s: Ditto.
* gas/i386/x86-64-se1.d: Ditto.
* gas/i386/x86-64-se1.s: Ditto.
opcodes/
* i386-dis.c (rm_table): Add encls, enclu.
* i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
(cpu_flags): Add CpuSE1.
* i386-opc.h (enum): Add CpuSE1.
(i386_cpu_flags): Add cpuse1.
* i386-opc.tbl: Add encls, enclu.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
Diffstat (limited to 'opcodes/i386-opc.tbl')
| -rw-r--r-- | opcodes/i386-opc.tbl | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index fbf0986..9f290a5 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -4314,3 +4314,10 @@ xsavec, 1, 0xfc7, 0x4, 2, CpuXSAVEC, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No xsavec64, 1, 0xfc7, 0x4, 2, CpuXSAVEC|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } // XSAVEC instructions end. + +// SGX instructions. + +encls, 0, 0xf01cf, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +enclu, 0, 0xf01d7, None, 3, CpuSE1, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// SGX instructions end. |