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| author | Jan Beulich <jbeulich@suse.com> | 2019-11-07 09:29:14 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2019-11-07 09:29:14 +0100 |
| commit | 142861dfd5b55fe4440c35351a068dcde4ad8ce9 (patch) | |
| tree | 82f0a734706af0d57cd3e46d045d92e0bda78680 /opcodes/i386-opc.tbl | |
| parent | 081e283fafb415b4e37f2ac1d5f945ad0b61e282 (diff) | |
| download | gdb-142861dfd5b55fe4440c35351a068dcde4ad8ce9.zip gdb-142861dfd5b55fe4440c35351a068dcde4ad8ce9.tar.gz gdb-142861dfd5b55fe4440c35351a068dcde4ad8ce9.tar.bz2 | |
x86: support further AMD Zen2 instructions
Both RDPRU and MCOMMIT have been publicly documented meanwhile:
https://www.amd.com/system/files/TechDocs/24594.pdf.
Diffstat (limited to 'opcodes/i386-opc.tbl')
| -rw-r--r-- | opcodes/i386-opc.tbl | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 21a6357..115c6f1 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -4767,3 +4767,15 @@ vp2intersectd, 3, 0xf268, None, 1, CpuAVX512_VP2INTERSECT, Modrm|VexOpcode|VexVV vp2intersectq, 3, 0xf268, None, 1, CpuAVX512_VP2INTERSECT, Modrm|VexOpcode|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } // VP2INTERSECT instructions end. + +// MCOMMIT instruction + +mcommit, 0, 0xf30f01fa, None, 3, CpuMCOMMIT, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// MCOMMIT instruction end + +// RDPRU instruction + +rdpru, 0, 0x0f01fd, None, 3, CpuRDPRU, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } + +// RDPRU instruction end |