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| author | Igor Tsimbalist <igor.v.tsimbalist@intel.com> | 2017-10-20 22:52:59 +0300 |
|---|---|---|
| committer | Igor Tsimbalist <igor.v.tsimbalist@intel.com> | 2017-10-23 15:58:07 +0300 |
| commit | 53467f5707ec796c0490d55e74854258a78013f8 (patch) | |
| tree | da0d8ffc09bed88b35d42d7bc3acb00020a8b044 /opcodes/i386-opc.h | |
| parent | f6af9f3428fa86030ba8ecd2da7d11e4ee1ed989 (diff) | |
| download | gdb-53467f5707ec796c0490d55e74854258a78013f8.zip gdb-53467f5707ec796c0490d55e74854258a78013f8.tar.gz gdb-53467f5707ec796c0490d55e74854258a78013f8.tar.bz2 | |
Enable Intel AVX512_VBMI2 instructions.
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .avx512_vbmi2.
(cpu_noarch): noavx512_vbmi2.
* doc/c-i386.texi: Document .avx512_vbmi2, noavx512_vbmi2.
* testsuite/gas/i386/i386.exp: Add AVX512_VBMI2 tests.
* testsuite/gas/i386/avx512vbmi2-intel.d: New test.
* testsuite/gas/i386/avx512vbmi2.d: Likewise.
* testsuite/gas/i386/avx512vbmi2.s: Likewise.
* testsuite/gas/i386/avx512vbmi2_vl-intel.d: Likewise.
* testsuite/gas/i386/avx512vbmi2_vl.d: Likewise.
* testsuite/gas/i386/avx512vbmi2_vl.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2_vl-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2_vl.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2_vl.s: Likewise.
opcodes/
* i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
Define EXbScalar and EXwScalar for OP_EX.
(enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
(enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
(intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
(OP_E_memory): Likewise.
* i386-dis-evex.h: Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_VBMI2.
* i386-opc.h (enum): Add CpuAVX512_VBMI2.
(i386_cpu_flags): Add cpuavx512_vbmi2.
* i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
Diffstat (limited to 'opcodes/i386-opc.h')
| -rw-r--r-- | opcodes/i386-opc.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index ccc774a..f677c5c 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -198,6 +198,8 @@ enum CpuAVX512_4VNNIW, /* Intel AVX-512 VPOPCNTDQ Instructions support required. */ CpuAVX512_VPOPCNTDQ, + /* Intel AVX-512 VBMI2 Instructions support required. */ + CpuAVX512_VBMI2, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -235,9 +237,9 @@ enum /* If you get a compiler error for zero width of the unused field, comment it out. */ -#if 0 + #define CpuUnused (CpuMax + 1) -#endif + /* We can check if an instruction is available with array instead of bitfield. */ @@ -328,6 +330,7 @@ typedef union i386_cpu_flags unsigned int cpuavx512_4fmaps:1; unsigned int cpuavx512_4vnniw:1; unsigned int cpuavx512_vpopcntdq:1; + unsigned int cpuavx512_vbmi2:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; |