binutils/

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* dwarf.c (dwarf_regnames_i386): Add AVX registers.
	(dwarf_regnames_x86_64): Likewise.

gas/

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx.

	* doc/c-i386.texi: Add avx, aes, clmul and fma to -march=.
	Document -msse2avx, .avx, .aes, .clmul and .fma.

	* config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New.
	(vex_prefix): Likewise.
	(sse2avx): Likewise.
	(CPU_FLAGS_ARCH_MATCH): Likewise.
	(CPU_FLAGS_64BIT_MATCH): Likewise.
	(CPU_FLAGS_32BIT_MATCH): Likewise.
	(CPU_FLAGS_PERFECT_MATCH): Likewise.
	(regymm): Likewise.
	(vex_imm4): Likewise.
	(fits_in_imm4): Likewise.
	(build_vex_prefix): Likewise.
	(VEX_check_operands): Likewise.
	(bad_implicit_operand): Likewise.
	(OPTION_MSSE2AVX): Likewise.
	(T_YMMWORD): Likewise.
	(_i386_insn): Add vex.
	(cpu_arch): Add .avx, .aes, .clmul and .fma.
	(cpu_flags_match): Changed to take a pointer to const template.
	Enable encoding SSE instructions with VEX prefix for -msse2avx.
	(match_mem_size): Also check ymmword.
	(operand_type_match): Clear ymmword.
	(md_begin): Allow '_' in mnemonic.
	(type_names): Add OPERAND_TYPE_VEX_IMM4.
	(process_immext): Update assert.
	(md_assemble): Don't call process_immext if sse2avx and immext
	are true.  Call build_vex_prefix if vex is true.
	(parse_insn): Updated for cpu_flags_match.
	(swap_operands): Handle 5 operands.
	(match_template): Handle 5 operands. Updated for cpu_flags_match.
	Check regymm.  Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX.
	(process_suffix): Handle YMMWORD_MNEM_SUFFIX.
	(check_byte_reg): Check regymm.
	(process_operands): Duplicate the destination register for
	-msse2avx if needed.
	(build_modrm_byte): Updated for instructions with VEX encoding.
	(output_insn): Output VEX prefix if needed.
	(md_longopts): Add msse2avx.
	(md_parse_option): Handle OPTION_MSSE2AVX.
	(md_show_usage): Add avx, aes, clmul, fma and -msse2avx.
	(intel_e09): Support YMMWORD.
	(intel_e11): Likewise.
	(intel_get_token): Likewise.

gas/testsuite/

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes,
	x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx,
	x86-64-avx-intel and x86-64-inval-avx.

	* gas/cfi/cfi-i386.s: Add tests for AVX register maps.
	* gas/cfi/cfi-x86_64.s: Likewise.

	* gas/i386/aes.d: New.
	* gas/i386/aes.s: Likewise.
	* gas/i386/aes-intel.d: Likewise.
	* gas/i386/avx.d: Likewise.
	* gas/i386/avx.s: Likewise.
	* gas/i386/avx-intel.d: Likewise.
	* gas/i386/clmul.d: Likewise.
	* gas/i386/clmul-intel.d: Likewise.
	* gas/i386/clmul.s: Likewise.
	* gas/i386/i386.exp: Likewise.
	* gas/i386/inval-avx.l: Likewise.
	* gas/i386/inval-avx.s: Likewise.
	* gas/i386/sse2avx.d: Likewise.
	* gas/i386/sse2avx.s: Likewise.
	* gas/i386/x86-64-aes.d: Likewise.
	* gas/i386/x86-64-aes.s: Likewise.
	* gas/i386/x86-64-aes-intel.d: Likewise.
	* gas/i386/x86-64-avx.d: Likewise.
	* gas/i386/x86-64-avx.s: Likewise.
	* gas/i386/x86-64-avx-intel.d: Likewise.
	* gas/i386/x86-64-clmul.d: Likewise.
	* gas/i386/x86-64-clmul-intel.d: Likewise.
	* gas/i386/x86-64-clmul.s: Likewise.
	* gas/i386/x86-64-inval-avx.l: Likewise.
	* gas/i386/x86-64-inval-avx.s: Likewise.
	* gas/i386/x86-64-sse2avx.d: Likewise.
	* gas/i386/x86-64-sse2avx.s: Likewise.

	* gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA.
	* gas/i386/x86-64-arch-2.s: Likewise.

	* gas/i386/rexw.s: Add AVX tests.

	* gas/i386/x86-64-opcode-inval.s: Remove lds/les test.

	* gas/cfi/cfi-i386.d: Updated.
	* gas/cfi/cfi-x86_64.d: Likewise.
	* gas/i386/arch-10.d:  Likewise.
	* gas/i386/arch-10-1.l: Likewise.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/rexw.d: Likewise.
	* gas/i386/x86-64-arch-2.d: Likewise.
	* gas/i386/x86-64-opcode-inval.d: Likewise.
	* gas/i386/x86-64-opcode-inval-intel.d: Likewise.

include/opcode/

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (MAX_OPERANDS): Set to 5.
	(MAX_MNEM_SIZE): Changed to 20.

opcodes/

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_register): New.
	(OP_E_memory): Likewise.
	(OP_VEX): Likewise.
	(OP_EX_Vex): Likewise.
	(OP_EX_VexW): Likewise.
	(OP_XMM_Vex): Likewise.
	(OP_XMM_VexW): Likewise.
	(OP_REG_VexI4): Likewise.
	(PCLMUL_Fixup): Likewise.
	(VEXI4_Fixup): Likewise.
	(VZERO_Fixup): Likewise.
	(VCMP_Fixup): Likewise.
	(VPERMIL2_Fixup): Likewise.
	(rex_original): Likewise.
	(rex_ignored): Likewise.
	(Mxmm): Likewise.
	(XMM): Likewise.
	(EXxmm): Likewise.
	(EXxmmq): Likewise.
	(EXymmq): Likewise.
	(Vex): Likewise.
	(Vex128): Likewise.
	(Vex256): Likewise.
	(VexI4): Likewise.
	(EXdVex): Likewise.
	(EXqVex): Likewise.
	(EXVexW): Likewise.
	(EXdVexW): Likewise.
	(EXqVexW): Likewise.
	(XMVex): Likewise.
	(XMVexW): Likewise.
	(XMVexI4): Likewise.
	(PCLMUL): Likewise.
	(VZERO): Likewise.
	(VCMP): Likewise.
	(VPERMIL2): Likewise.
	(xmm_mode): Likewise.
	(xmmq_mode): Likewise.
	(ymmq_mode): Likewise.
	(vex_mode): Likewise.
	(vex128_mode): Likewise.
	(vex256_mode): Likewise.
	(USE_VEX_C4_TABLE): Likewise.
	(USE_VEX_C5_TABLE): Likewise.
	(USE_VEX_LEN_TABLE): Likewise.
	(VEX_C4_TABLE): Likewise.
	(VEX_C5_TABLE): Likewise.
	(VEX_LEN_TABLE): Likewise.
	(REG_VEX_XX): Likewise.
	(MOD_VEX_XXX): Likewise.
	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	(PREFIX_0F3A44): Likewise.
	(PREFIX_0F3ADF): Likewise.
	(PREFIX_VEX_XXX): Likewise.
	(VEX_OF): Likewise.
	(VEX_OF38): Likewise.
	(VEX_OF3A): Likewise.
	(VEX_LEN_XXX): Likewise.
	(vex): Likewise.
	(need_vex): Likewise.
	(need_vex_reg): Likewise.
	(vex_i4_done): Likewise.
	(vex_table): Likewise.
	(vex_len_table): Likewise.
	(OP_REG_VexI4): Likewise.
	(vex_cmp_op): Likewise.
	(pclmul_op): Likewise.
	(vpermil2_op): Likewise.
	(m_mode): Updated.
	(es_reg): Likewise.
	(PREFIX_0F38F0): Likewise.
	(PREFIX_0F3A60): Likewise.
	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
	and PREFIX_VEX_XXX entries.
	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
	PREFIX_0F3ADF.
	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
	Add MOD_VEX_XXX entries.
	(ckprefix): Initialize rex_original and rex_ignored.  Store the
	REX byte in rex_original.
	(get_valid_dis386): Handle the implicit prefix in VEX prefix
	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
	calling get_valid_dis386.  Use rex_original and rex_ignored when
	printing out REX.
	(putop): Handle "XY".
	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
	ymmq_mode.
	(OP_E_extended): Updated to use OP_E_register and
	OP_E_memory.
	(OP_XMM): Handle VEX.
	(OP_EX): Likewise.
	(XMM_Fixup): Likewise.
	(CMP_Fixup): Use ARRAY_SIZE.

	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
	(operand_type_init): Add OPERAND_TYPE_REGYMM and
	OPERAND_TYPE_VEX_IMM4.
	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
	VexImmExt and SSE2AVX.
	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.

	* i386-opc.h (CpuAVX): New.
	(CpuAES): Likewise.
	(CpuCLMUL): Likewise.
	(CpuFMA): Likewise.
	(Vex): Likewise.
	(Vex256): Likewise.
	(VexNDS): Likewise.
	(VexNDD): Likewise.
	(VexW0): Likewise.
	(VexW1): Likewise.
	(Vex0F): Likewise.
	(Vex0F38): Likewise.
	(Vex0F3A): Likewise.
	(Vex3Sources): Likewise.
	(VexImmExt): Likewise.
	(SSE2AVX): Likewise.
	(RegYMM): Likewise.
	(Ymmword): Likewise.
	(Vex_Imm4): Likewise.
	(Implicit1stXmm0): Likewise.
	(CpuXsave): Updated.
	(CpuLM): Likewise.
	(ByteOkIntel): Likewise.
	(OldGcc): Likewise.
	(Control): Likewise.
	(Unspecified): Likewise.
	(OTMax): Likewise.
	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
	vex3sources, veximmext and sse2avx.
	(i386_operand_type): Add regymm, ymmword and vex_imm4.

	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.

	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

1 files changed, 70 insertions, 7 deletions

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index d66f02b..4ea2ec4 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -80,10 +80,18 @@
 #define CpuSSE4_2	(CpuSSE4_1 + 1)
 /* SSE5 support required */
 #define CpuSSE5		(CpuSSE4_2 + 1)
+/* AVX support required */
+#define CpuAVX		(CpuSSE5 + 1)
 /* Xsave/xrstor New Instuctions support required */
-#define CpuXsave	(CpuSSE5 + 1)
+#define CpuXsave	(CpuAVX + 1)
+/* AES support required */
+#define CpuAES		(CpuXsave + 1)
+/* CLMUL support required */
+#define CpuCLMUL	(CpuAES + 1)
+/* FMA support required */
+#define CpuFMA		(CpuCLMUL + 1)
 /* 64bit support available, used by -march= in assembler.  */
-#define CpuLM		(CpuXsave + 1)
+#define CpuLM		(CpuFMA + 1)
 /* 64bit support required  */
 #define Cpu64		(CpuLM + 1)
 /* Not supported in the 64bit mode  */
@@ -131,7 +139,11 @@ typedef union i386_cpu_flags
       unsigned int cpusse4_1:1;
       unsigned int cpusse4_2:1;
       unsigned int cpusse5:1;
+      unsigned int cpuavx:1;
       unsigned int cpuxsave:1;
+      unsigned int cpuaes:1;
+      unsigned int cpuclmul:1;
+      unsigned int cpufma:1;
       unsigned int cpulm:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
@@ -198,8 +210,10 @@ typedef union i386_cpu_flags
 #define RegKludge		(IsString + 1)
 /* The first operand must be xmm0 */
 #define FirstXmm0		(RegKludge + 1)
+/* An implicit xmm0 as the first operand */
+#define Implicit1stXmm0		(FirstXmm0 + 1)
 /* BYTE is OK in Intel syntax. */
-#define ByteOkIntel		(FirstXmm0 + 1)
+#define ByteOkIntel		(Implicit1stXmm0 + 1)
 /* Convert to DWORD */
 #define ToDword			(ByteOkIntel + 1)
 /* Convert to QWORD */
@@ -221,8 +235,34 @@ typedef union i386_cpu_flags
 #define Drexv			(Drex + 1)
 /* special DREX for comparisons */
 #define Drexc			(Drexv + 1)
+/* insn has VEX prefix. */
+#define Vex			(Drexc + 1)
+/* insn has 256bit VEX prefix. */
+#define Vex256			(Vex + 1)
+/* insn has VEX NDS. Register-only source is encoded in Vex
+   prefix. */
+#define VexNDS			(Vex256 + 1)
+/* insn has VEX NDD. Register destination is encoded in Vex
+   prefix. */
+#define VexNDD			(VexNDS + 1)
+/* insn has VEX W0. */
+#define VexW0			(VexNDD + 1)
+/* insn has VEX W1. */
+#define VexW1			(VexW0 + 1)
+/* insn has VEX 0x0F opcode prefix. */
+#define Vex0F			(VexW1 + 1)
+/* insn has VEX 0x0F38 opcode prefix. */
+#define Vex0F38			(Vex0F + 1)
+/* insn has VEX 0x0F3A opcode prefix. */
+#define Vex0F3A			(Vex0F38 + 1)
+/* insn has VEX prefix with 3 soures. */
+#define Vex3Sources		(Vex0F3A + 1)
+/* instruction has VEX 8 bit imm */
+#define VexImmExt		(Vex3Sources + 1)
+/* SSE to AVX support required */
+#define SSE2AVX			(VexImmExt + 1)
 /* Compatible with old (<= 2.8.1) versions of gcc  */
-#define OldGcc			(Drexc + 1)
+#define OldGcc			(SSE2AVX + 1)
 /* AT&T mnemonic.  */
 #define ATTMnemonic		(OldGcc + 1)
 /* AT&T syntax.  */
@@ -260,6 +300,7 @@ typedef struct i386_opcode_modifier
   unsigned int isstring:1;
   unsigned int regkludge:1;
   unsigned int firstxmm0:1;
+  unsigned int implicit1stxmm0:1;
   unsigned int byteokintel:1;
   unsigned int todword:1;
   unsigned int toqword:1;
@@ -272,6 +313,18 @@ typedef struct i386_opcode_modifier
   unsigned int drex:1;
   unsigned int drexv:1;
   unsigned int drexc:1;
+  unsigned int vex:1;
+  unsigned int vex256:1;
+  unsigned int vexnds:1;
+  unsigned int vexndd:1;
+  unsigned int vexw0:1;
+  unsigned int vexw1:1;
+  unsigned int vex0f:1;
+  unsigned int vex0f38:1;
+  unsigned int vex0f3a:1;
+  unsigned int vex3sources:1;
+  unsigned int veximmext:1;
+  unsigned int sse2avx:1;
   unsigned int oldgcc:1;
   unsigned int attmnemonic:1;
   unsigned int attsyntax:1;
@@ -294,8 +347,10 @@ typedef struct i386_opcode_modifier
 #define RegMMX			(FloatReg + 1)
 /* SSE register */
 #define RegXMM			(RegMMX + 1)
+/* AVX registers */
+#define RegYMM			(RegXMM + 1)
 /* Control register */
-#define Control			(RegXMM + 1)
+#define Control			(RegYMM + 1)
 /* Debug register */
 #define Debug			(Control + 1)
 /* Test register */
@@ -371,13 +426,18 @@ typedef struct i386_opcode_modifier
 #define Tbyte			(Qword + 1)
 /* XMMWORD memory. */
 #define Xmmword			(Tbyte + 1)
+/* YMMWORD memory. */
+#define Ymmword			(Xmmword + 1)
 /* Unspecified memory size.  */
-#define Unspecified		(Xmmword + 1)
+#define Unspecified		(Ymmword + 1)
 /* Any memory size.  */
 #define Anysize			(Unspecified  + 1)
 
+/* VEX 4 bit immediate */
+#define Vex_Imm4		(Anysize + 1)
+
 /* The last bitfield in i386_operand_type.  */
-#define OTMax			Anysize
+#define OTMax			Vex_Imm4
 
 #define OTNumOfUints \
   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
@@ -399,6 +459,7 @@ typedef union i386_operand_type
       unsigned int floatreg:1;
       unsigned int regmmx:1;
       unsigned int regxmm:1;
+      unsigned int regymm:1;
       unsigned int control:1;
       unsigned int debug:1;
       unsigned int test:1;
@@ -432,8 +493,10 @@ typedef union i386_operand_type
       unsigned int qword:1;
       unsigned int tbyte:1;
       unsigned int xmmword:1;
+      unsigned int ymmword:1;
       unsigned int unspecified:1;
       unsigned int anysize:1;
+      unsigned int vex_imm4:1;
 #ifdef OTUnused
       unsigned int unused:(OTNumOfBits - OTUnused);
 #endif