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authorDwarakanath Rajagopal <dwarak.rajagopal@amd.com>2009-05-22 15:57:25 +0000
committerDwarakanath Rajagopal <dwarak.rajagopal@amd.com>2009-05-22 15:57:25 +0000
commitc1e679ec0a47d39a315c7adb5e28106fcb27beac (patch)
tree06b794df6756a93e6ba6cc997ee9de2e5f3faccc /opcodes/i386-opc.h
parentcb150213b276655b6c200cc2c61b408f6264d777 (diff)
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<gas changes>
2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * config/tc-i386.c (process_drex): Delete. Remove SSE5 support. (build_modrm_byte): Remove DREX handling support. (DREX_*): Delete. (drex_byte): Delete. (md_assemble): Remove DREX handling support. (process_operands): Remove DREX, SSE5 support. (i386_insn): Remove DREX. <gas/testsuite changes> 2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * gas/i386/i386.exp: Remove SSE5 tests. * gas/i386/x86-64-sse5.s: Delete. Remove SSE5 tests. * gas/i386/x86-64-sse5.d: Ditto. * gas/i386/arch-10-1.l: Remove SSE5 tests. * gas/i386/arch-10-2.l: Ditto. * gas/i386/arch-10-3.l: Ditto. * gas/i386/arch-10-4.l: Ditto. * gas/i386/arch-10.d: Ditto. * gas/i386/arch-10.s: Ditto. * gas/i386/arch-4.s: Delete. Remove SSE5 tests. * gas/i386/arch-4.d: Ditto. * gas/i386/arch-8.s: Ditto. * gas/i386/arch-8.d: Ditto. * gas/i386/arch-2.s: Remove SSE5 tests. * gas/i386/arch-2.d: Remove SSE5 tests. * gas/i386/x86-64-arch-2.s: Ditto. <opcodes changes> 2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * i386-opc.h (Cpusse5): Delete. (i386_cpu_flags): Delete. * i386-gen.c: Remove CpuSSE5, Drex, Drexv and Drexc. * i386-opc.tbl: Remove SSE5 instructions. * i386-tbl.h: Regenerate. * i386-init.h: Regenerate. * i386-dis.c (OP_E_memeory, OP_E_extended): Remove drex handling. (print_drex_arg): Delete. (OP_DREX4): Delete. (OP_DREX3): Delete. (OP_DREX_ICMP): Delete. (OP_DREX_FCMP): Delete. (DREX_*): Delete. (THREE_BYTE_0F24, THREE_BYTE_0F25, THREE_BYTE_0f7B): Delete.
Diffstat (limited to 'opcodes/i386-opc.h')
-rw-r--r--opcodes/i386-opc.h17
1 files changed, 3 insertions, 14 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index a3ff4bf..08e5a57 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -76,10 +76,8 @@
#define CpuSSE4_1 (CpuABM + 1)
/* SSE4.2 support required */
#define CpuSSE4_2 (CpuSSE4_1 + 1)
-/* SSE5 support required */
-#define CpuSSE5 (CpuSSE4_2 + 1)
/* AVX support required */
-#define CpuAVX (CpuSSE5 + 1)
+#define CpuAVX (CpuSSE4_2 + 1)
/* Xsave/xrstor New Instuctions support required */
#define CpuXsave (CpuAVX + 1)
/* AES support required */
@@ -141,7 +139,6 @@ typedef union i386_cpu_flags
unsigned int cpuabm:1;
unsigned int cpusse4_1:1;
unsigned int cpusse4_2:1;
- unsigned int cpusse5:1;
unsigned int cpuavx:1;
unsigned int cpuxsave:1;
unsigned int cpuaes:1;
@@ -239,13 +236,8 @@ typedef union i386_cpu_flags
#define Rex64 (NoRex64 + 1)
/* deprecated fp insn, gets a warning */
#define Ugh (Rex64 + 1)
-#define Drex (Ugh + 1)
-/* instruction needs DREX with multiple encodings for memory ops */
-#define Drexv (Drex + 1)
-/* special DREX for comparisons */
-#define Drexc (Drexv + 1)
/* insn has VEX prefix. */
-#define Vex (Drexc + 1)
+#define Vex (Ugh + 1)
/* insn has 256bit VEX prefix. */
#define Vex256 (Vex + 1)
/* insn has VEX NDS. Register-only source is encoded in Vex prefix.
@@ -323,9 +315,6 @@ typedef struct i386_opcode_modifier
unsigned int norex64:1;
unsigned int rex64:1;
unsigned int ugh:1;
- unsigned int drex:1;
- unsigned int drexv:1;
- unsigned int drexc:1;
unsigned int vex:1;
unsigned int vex256:1;
unsigned int vexnds:1;
@@ -535,7 +524,7 @@ typedef struct template
This field is also used to store the 8-bit opcode suffix for the
AMD 3DNow! instructions.
If this template has no extension opcode (the usual case) use None
- Instructions with Drex use this to specify 2 bits for OC */
+ Instructions */
unsigned int extension_opcode;
#define None 0xffff /* If no extension_opcode is possible. */