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| author | Sebastian Pop <sebastian.pop@amd.com> | 2009-11-05 23:40:05 +0000 |
|---|---|---|
| committer | Sebastian Pop <sebastian.pop@amd.com> | 2009-11-05 23:40:05 +0000 |
| commit | f88c9eb030684877952d1316567fdc461d69772a (patch) | |
| tree | e7da5818868361faa92bcf0b99d702d2b0b967dd /opcodes/i386-opc.h | |
| parent | d85a05f07f9f01c6b7e0e84491ca7972a621b85b (diff) | |
| download | gdb-f88c9eb030684877952d1316567fdc461d69772a.zip gdb-f88c9eb030684877952d1316567fdc461d69772a.tar.gz gdb-f88c9eb030684877952d1316567fdc461d69772a.tar.bz2 | |
2009-11-05 Sebastian Pop <sebastian.pop@amd.com>
Quentin Neill <quentin.neill@amd.com>
* gas/config/tc-i386.c (cpu_arch): Add CPU_LWP_FLAGS.
(build_vex_prefix): Handle xop09 and xop0a.
(build_modrm_byte): Handle vexlwp.
(md_show_usage): Add lwp.
* gas/doc/c-i386.texi (i386-LWP): New section.
* gas/testsuite/gas/i386/i386.exp: Run x86-64-lwp in 64-bit mode,
run lwp in 32-bit mode.
* gas/testsuite/gas/i386/x86-64-lwp.d: New.
* gas/testsuite/gas/i386/x86-64-lwp.s: New.
* gas/testsuite/gas/i386/lwp.d: New.
* gas/testsuite/gas/i386/lwp.s: New.
* opcodes/i386-dis.c (OP_LWPCB_E): New.
(OP_LWP_E): New.
(OP_LWP_I): New.
(USE_XOP_8F_TABLE): New.
(XOP_8F_TABLE): New.
(REG_XOP_LWPCB): New.
(REG_XOP_LWP): New.
(XOP_09): New.
(XOP_0A): New.
(reg_table): Redirect REG_8F to XOP_8F_TABLE.
Add entries for REG_XOP_LWPCB and REG_XOP_LWP.
(xop_table): New.
(get_valid_dis386): Handle USE_XOP_8F_TABLE.
Use the offsets VEX_0F, VEX_0F38, and VEX_0F3A instead of their values
to access to the vex_table.
(OP_LWPCB_E): New.
(OP_LWP_E): New.
(OP_LWP_I): New.
* opcodes/i386-gen.c (cpu_flag_init): Add CPU_LWP_FLAGS, CpuLWP.
(cpu_flags): Add CpuLWP.
(opcode_modifiers): Add VexLWP, XOP09, and XOP0A.
* opcodes/i386-opc.h (CpuLWP): New.
(i386_cpu_flags): Add bit cpulwp.
(VexLWP): New.
(XOP09): New.
(XOP0A): New.
(i386_opcode_modifier): Add vexlwp, xop09, and xop0a.
* opcodes/i386-opc.tbl (llwpcb): Added.
(lwpval): Added.
(lwpins): Added.
Diffstat (limited to 'opcodes/i386-opc.h')
| -rw-r--r-- | opcodes/i386-opc.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 6c48dbc..f8de8cd 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -102,6 +102,8 @@ enum CpuFMA, /* FMA4 support required */ CpuFMA4, + /* LWP support required */ + CpuLWP, /* MOVBE Instuction support required */ CpuMovbe, /* EPT Instructions required */ @@ -168,6 +170,7 @@ typedef union i386_cpu_flags unsigned int cpupclmul:1; unsigned int cpufma:1; unsigned int cpufma4:1; + unsigned int cpulwp:1; unsigned int cpumovbe:1; unsigned int cpuept:1; unsigned int cpurdtscp:1; @@ -273,6 +276,9 @@ enum VexNDS, /* insn has VEX NDD. Register destination is encoded in Vex prefix. */ VexNDD, + /* insn has VEX NDD. Register destination is encoded in Vex prefix + and one of the operands can access a memory location. */ + VexLWP, /* insn has VEX W0. */ VexW0, /* insn has VEX W1. */ @@ -283,6 +289,10 @@ enum Vex0F38, /* insn has VEX 0x0F3A opcode prefix. */ Vex0F3A, + /* insn has XOP 0x09 opcode prefix. */ + XOP09, + /* insn has XOP 0x0A opcode prefix. */ + XOP0A, /* insn has VEX prefix with 3 soures. */ Vex3Sources, /* instruction has VEX 8 bit imm */ @@ -345,11 +355,14 @@ typedef struct i386_opcode_modifier unsigned int vex:2; unsigned int vexnds:1; unsigned int vexndd:1; + unsigned int vexlwp:1; unsigned int vexw0:1; unsigned int vexw1:1; unsigned int vex0f:1; unsigned int vex0f38:1; unsigned int vex0f3a:1; + unsigned int xop09:1; + unsigned int xop0a:1; unsigned int vex3sources:1; unsigned int veximmext:1; unsigned int sse2avx:1; |