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| author | H.J. Lu <hjl.tools@gmail.com> | 2009-12-19 18:36:27 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2009-12-19 18:36:27 +0000 |
| commit | 2426c15ff89cabccb43c20dda1d7696017c48875 (patch) | |
| tree | ceecdf81527dcf9cafeb96e4629fad8d0804e3ea /opcodes/i386-opc.h | |
| parent | e946488510bafc86fde2f58a6da1709b20b61bef (diff) | |
| download | gdb-2426c15ff89cabccb43c20dda1d7696017c48875.zip gdb-2426c15ff89cabccb43c20dda1d7696017c48875.tar.gz gdb-2426c15ff89cabccb43c20dda1d7696017c48875.tar.bz2 | |
Replace VexNDS, VexNDD and VexLWP with VexVVVV.
gas/
2009-12-19 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_operands): Check vexvvvv instead
of vexnds and vexndd.
(build_modrm_byte): Check vexvvvv instead of vexnds, vexndd
and vexlwp.
opcodes/
2009-12-19 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove VexNDS, VexNDD and
VexLWP. Add VexVVVV.
* i386-opc.h (VexNDS): Removed.
(VexNDD): Likewise.
(VexLWP): Likewise.
(VEXXDS): New.
(VEXNDD): Likewise.
(VEXLWP): Likewise.
(VexVVVV): Likewise.
(i386_opcode_modifier): Remove vexnds, vexndd and vexlwp.
Add vexvvvv.
* i386-opc.tbl: Replace VexNDS with VexVVVV=1, VexNDD with
VexVVVV=2 and VexLWP with VexVVVV=3.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-opc.h')
| -rw-r--r-- | opcodes/i386-opc.h | 30 |
1 files changed, 18 insertions, 12 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 1b1da67..523d390 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -275,15 +275,23 @@ enum #define VEX128 1 #define VEX256 2 Vex, - /* insn has VEX NDS. Register-only source is encoded in Vex prefix. - We use VexNDS on insns with VEX DDS since the register-only source - is the second source register. */ - VexNDS, - /* insn has VEX NDD. Register destination is encoded in Vex prefix. */ - VexNDD, - /* insn has VEX NDD. Register destination is encoded in Vex prefix - and one of the operands can access a memory location. */ - VexLWP, + /* How to encode VEX.vvvv: + 0: VEX.vvvv must be 1111b. + 1: VEX.DNS. Register-only source is encoded in VEX.vvvv where + the content of source registers will be preserved. + VEX.DDS. The second register operand is encoded in VEX.vvvv + where the content of first source register will be overwritten + by the result. + For assembler, there are no difference between VEX.DNS and + VEX.DDS. + 2. VEX.NDD. Register destination is encoded in VEX.vvvv. + 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one + of the operands can access a memory location. + */ +#define VEXXDS 1 +#define VEXNDD 2 +#define VEXLWP 3 + VexVVVV, /* How the VEX.W bit is used: 0: Set by the REX.W bit. 1: VEX.W0. Should always be 0. @@ -373,9 +381,7 @@ typedef struct i386_opcode_modifier unsigned int rex64:1; unsigned int ugh:1; unsigned int vex:2; - unsigned int vexnds:1; - unsigned int vexndd:1; - unsigned int vexlwp:1; + unsigned int vexvvvv:2; unsigned int vexw:2; unsigned int vexopcode:3; unsigned int vexsources:2; |