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| author | Jan Beulich <jbeulich@suse.com> | 2019-11-08 09:04:53 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2019-11-08 09:04:53 +0100 |
| commit | 4a5c67ed841db42c7be13cb2991ece3b3fc4bf75 (patch) | |
| tree | 1fd1a44252fd896a35508f621c16725163ecd844 /opcodes/i386-opc.h | |
| parent | 00cee14fbad24453ff56656c5726ef5e4b0de588 (diff) | |
| download | gdb-4a5c67ed841db42c7be13cb2991ece3b3fc4bf75.zip gdb-4a5c67ed841db42c7be13cb2991ece3b3fc4bf75.tar.gz gdb-4a5c67ed841db42c7be13cb2991ece3b3fc4bf75.tar.bz2 | |
x86: convert Control/Debug/Test from bitfield to enumerator
This is to further shrink the operand type representation.
Diffstat (limited to 'opcodes/i386-opc.h')
| -rw-r--r-- | opcodes/i386-opc.h | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index e8cf895..2417c08 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -710,6 +710,9 @@ enum operand_class ClassNone, Reg, /* GPRs and FP regs, distinguished by operand size */ SReg, /* Segment register */ + RegCR, /* Control register */ + RegDR, /* Debug register */ + RegTR, /* Test register */ }; /* Position of operand_type bits. */ @@ -724,12 +727,6 @@ enum RegSIMD, /* Vector Mask registers */ RegMask, - /* Control register */ - Control, - /* Debug register */ - Debug, - /* Test register */ - Test, /* 1 bit immediate */ Imm1, /* 8 bit immediate */ @@ -820,9 +817,6 @@ typedef union i386_operand_type unsigned int regmmx:1; unsigned int regsimd:1; unsigned int regmask:1; - unsigned int control:1; - unsigned int debug:1; - unsigned int test:1; unsigned int imm1:1; unsigned int imm8:1; unsigned int imm8s:1; |