diff options
| author | Cui, Lili <lili.cui@intel.com> | 2024-05-06 14:15:49 +0800 |
|---|---|---|
| committer | Cui, Lili <lili.cui@intel.com> | 2024-05-06 18:16:42 +0800 |
| commit | f2a3a8814da7c18144e517c11ac84ef6799b0534 (patch) | |
| tree | 87c21200ba98da332d3017f2fb008580eba0a4ac /opcodes/i386-opc.h | |
| parent | f4c1c984bf02e9326b8a2141702beb1542103d70 (diff) | |
| download | gdb-f2a3a8814da7c18144e517c11ac84ef6799b0534.zip gdb-f2a3a8814da7c18144e517c11ac84ef6799b0534.tar.gz gdb-f2a3a8814da7c18144e517c11ac84ef6799b0534.tar.bz2 | |
x86: Use vexvvvv as the switch state to encode the vvvv register
Use vexvvvv as the switch state, and replace VexVVVV with Src1VVVV.
Src1VVVV means using VEX.vvvv encodes the first source register
operand. The old logic did not check vexvvvv first, which made the
logic here very complicated.
gas/ChangeLog:
* config/tc-i386.c (optimize_encoding): Replaced 1 with Src1VVVV.
(build_modrm_byte): Used vexvvvv to encode the vvvv register.
(s_insn): Replaced 1 with Src1VVVV.
opcodes/ChangeLog:
* i386-opc.h (VexVVVV_DST): Adjusted the value.
(Src1VVVV): New.
* i386-opc.tbl: Replaced part VexVVVV with Src1VVVV.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-opc.h')
| -rw-r--r-- | opcodes/i386-opc.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index ce54c9d..4ae87a3 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -639,11 +639,12 @@ enum #define VEXScalar 3 Vex, /* How to encode VEX.vvvv: - 0: VEX.vvvv must be 1111b. - 1: VEX.vvvv encodes one of the src register operands. - 2: VEX.vvvv encodes the dest register operand. + 1: VEX.vvvv encodes the src1 register operand. + 3: VEX.vvvv encodes the dest register operand. */ -#define VexVVVV_DST 2 +#define VexVVVV_SRC1 1 +#define VexVVVV_DST 3 + VexVVVV, /* How the VEX.W bit is used: 0: Set by the REX.W bit. |