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authorJan Beulich <jbeulich@suse.com>2023-09-15 09:57:05 +0200
committerJan Beulich <jbeulich@suse.com>2023-09-15 09:57:05 +0200
commitda5f9eb43fd792ec2c9366262ba2bf3becb6adb1 (patch)
tree80129b78ace0e3832da0de8c58d7aa6c80bbf7b3 /opcodes/i386-opc.h
parentc0260ac61915b053c1a2539797ed5fd06eb99ac6 (diff)
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x86: fold CpuLM and Cpu64
Now that CpuLM is used solely in cpu_arch_flags and cpu_arch[] while Cpu64 is solely used in insn templates, they no longer need to be treated different from other "ordinary" flags; the only "unusual" one left if CpuNo64. Fold both, leaving just Cpu64.
Diffstat (limited to 'opcodes/i386-opc.h')
-rw-r--r--opcodes/i386-opc.h11
1 files changed, 4 insertions, 7 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 045277e..149ae0e 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -147,8 +147,6 @@ enum i386_cpu
CpuVMFUNC,
/* Intel MPX Instructions required */
CpuMPX,
- /* 64bit support available, used by -march= in assembler. */
- CpuLM,
/* RDRSEED instruction required. */
CpuRDSEED,
/* Multi-presisionn add-carry instructions are required. */
@@ -309,6 +307,8 @@ enum i386_cpu
Cpu3dnow,
/* 3dnow! Extensions support required */
Cpu3dnowA,
+ /* 64bit support required */
+ Cpu64,
/* AVX support required */
CpuAVX,
/* HLE support required */
@@ -317,8 +317,6 @@ enum i386_cpu
CpuAVX512F,
/* Intel AVX-512 VL Instructions support required. */
CpuAVX512VL,
- /* 64bit support required */
- Cpu64,
/* Not supported in the 64bit mode */
CpuNo64,
@@ -349,12 +347,12 @@ enum i386_cpu
cpu387:1, \
cpu3dnow:1, \
cpu3dnowa:1, \
+ cpu64:1, \
cpuavx:1, \
cpuhle:1, \
cpuavx512f:1, \
cpuavx512vl:1, \
- /* NOTE: These two fields need to remain last and in this order. */ \
- cpu64:1, \
+ /* NOTE: This field needs to remain last. */ \
cpuno64:1
typedef union i386_cpu_attr
@@ -435,7 +433,6 @@ typedef union i386_cpu_flags
unsigned int cpuinvpcid:1;
unsigned int cpuvmfunc:1;
unsigned int cpumpx:1;
- unsigned int cpulm:1;
unsigned int cpurdseed:1;
unsigned int cpuadx:1;
unsigned int cpuprfchw:1;