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| author | Cui, Lili <lili.cui@intel.com> | 2024-05-06 14:16:13 +0800 |
|---|---|---|
| committer | Cui, Lili <lili.cui@intel.com> | 2024-05-06 18:21:28 +0800 |
| commit | 0820c9f5fc13047b4b25361d6d3bb0ceb2a611d8 (patch) | |
| tree | e162ae8ce3c2e1820cb7a3f1d3edde9a9d8bd546 /opcodes/i386-opc.h | |
| parent | f2a3a8814da7c18144e517c11ac84ef6799b0534 (diff) | |
| download | gdb-0820c9f5fc13047b4b25361d6d3bb0ceb2a611d8.zip gdb-0820c9f5fc13047b4b25361d6d3bb0ceb2a611d8.tar.gz gdb-0820c9f5fc13047b4b25361d6d3bb0ceb2a611d8.tar.bz2 | |
x86: Drop SwapSources
gas/ChangeLog:
* config/tc-i386.c (build_modrm_byte): Dropped the use of
SWAP_SOURCES to encode the vvvv register.
opcodes/ChangeLog:
* i386-opc.h (SWAP_SOURCES): Dropped.
(NO_DEFAULT_MASK): Adjusted the value.
(ADDR_PREFIX_OP_REG): Ditto.
(DISTINCT_DEST): Ditto.
(IMPLICIT_STACK_OP): Ditto.
(VexVVVV_SRC2): New.
* i386-opc.tbl: Dropped SwapSources and replaced its VexVVVV
with Src1VVVV.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-opc.h')
| -rw-r--r-- | opcodes/i386-opc.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 4ae87a3..fa482ca 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -570,17 +570,15 @@ enum It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3). */ #define IMPLICIT_QUAD_GROUP 5 - /* Two source operands are swapped. */ -#define SWAP_SOURCES 6 /* Default mask isn't allowed. */ -#define NO_DEFAULT_MASK 7 +#define NO_DEFAULT_MASK 6 /* Address prefix changes register operand */ -#define ADDR_PREFIX_OP_REG 8 +#define ADDR_PREFIX_OP_REG 7 /* Instrucion requires that destination must be distinct from source registers. */ -#define DISTINCT_DEST 9 +#define DISTINCT_DEST 8 /* Instruction updates stack pointer implicitly. */ -#define IMPLICIT_STACK_OP 10 +#define IMPLICIT_STACK_OP 9 OperandConstraint, /* instruction ignores operand size prefix and in Intel mode ignores mnemonic size suffix check. */ @@ -640,9 +638,11 @@ enum Vex, /* How to encode VEX.vvvv: 1: VEX.vvvv encodes the src1 register operand. + 2: VEX.vvvv encodes the src2 register operand. 3: VEX.vvvv encodes the dest register operand. */ #define VexVVVV_SRC1 1 +#define VexVVVV_SRC2 2 #define VexVVVV_DST 3 VexVVVV, |