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| author | H.J. Lu <hjl.tools@gmail.com> | 2007-05-03 21:07:16 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2007-05-03 21:07:16 +0000 |
| commit | 20592a94ff6918ed50c73726379a196357b96697 (patch) | |
| tree | 5dd253f56a01515d5f4d5de84f07e79e7999bfba /opcodes/i386-opc.c | |
| parent | 93c0f4a4976caa0ba7331c4ec0d5e770e3d27576 (diff) | |
| download | gdb-20592a94ff6918ed50c73726379a196357b96697.zip gdb-20592a94ff6918ed50c73726379a196357b96697.tar.gz gdb-20592a94ff6918ed50c73726379a196357b96697.tar.bz2 | |
gas/
2007-05-03 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (match_template): Don't explicitly check
suffix for crc32 in Intel mode.
(process_suffix): Issue an error for crc32 if the operand size
is ambiguous.
gas/testsuite/
2007-05-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/crc32-intel.d: Updated.
* gas/i386/crc32.d: Likewise.
* gas/i386/sse4_2.d: Likewise.
* gas/i386/x86-64-crc32-intel.d: Likewise.
* gas/i386/x86-64-crc32.d: Likewise.
* gas/i386/x86-64-sse4_2.d: Likewise.
* gas/i386/crc32.s: Remove crc32 instructions with ambiguous
operand size and suffix in crc32 instructions in Intel mode.
* gas/i386/x86-64-crc32.s: Likewise.
* gas/i386/sse4_2.s: Remove crc32 instructions with ambiguous
operand size.
* gas/i386/x86-64-sse4_2.s: Likewise.
* gas/i386/i386.exp: Run inval-crc32 and x86-64-inval-crc32.
* gas/i386/inval-crc32.l: New.
* gas/i386/inval-crc32.s: Likewise.
* gas/i386/x86-64-inval-crc32.l: Likewise.
* gas/i386/x86-64-inval-crc32.s: Likewise.
opcodes/
2007-05-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (CRC32_Fixup): Don't print suffix in Intel mode.
* i386-opc.c (i386_optab): Remove IgnoreSize and correct operand
type for crc32.
Diffstat (limited to 'opcodes/i386-opc.c')
| -rw-r--r-- | opcodes/i386-opc.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/opcodes/i386-opc.c b/opcodes/i386-opc.c index e03152c..b0f4884 100644 --- a/opcodes/i386-opc.c +++ b/opcodes/i386-opc.c @@ -1444,10 +1444,10 @@ const template i386_optab[] = {"pcmpistrm", 3, 0x660f3a62,X, CpuSSE4_2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, /* We put non-8bit version before 8bit so that crc32 with memory operand defaults to non-8bit. */ -{"crc32", 2, 0xf20f38f1,X, CpuSSE4_2, wl_Suf|Modrm, { WordReg|WordMem, Reg32, 0 } }, -{"crc32", 2, 0xf20f38f1,X, CpuSSE4_2|Cpu64, q_Suf|IgnoreSize|Modrm|Rex64, { Reg64|LLongMem, Reg64, 0 } }, +{"crc32", 2, 0xf20f38f1,X, CpuSSE4_2, wl_Suf|Modrm, { Reg16|Reg32|ShortMem|LongMem, Reg32, 0 } }, +{"crc32", 2, 0xf20f38f1,X, CpuSSE4_2|Cpu64, q_Suf|Modrm|Rex64, { Reg64|LLongMem, Reg64, 0 } }, {"crc32", 2, 0xf20f38f0,X, CpuSSE4_2, b_Suf|Modrm, { Reg8|ByteMem, Reg32, 0 } }, -{"crc32", 2, 0xf20f38f0,X, CpuSSE4_2|Cpu64, b_Suf|IgnoreSize|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0 } }, +{"crc32", 2, 0xf20f38f0,X, CpuSSE4_2|Cpu64, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0 } }, /* AMD 3DNow! instructions. */ |