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| author | H.J. Lu <hjl.tools@gmail.com> | 2020-06-26 08:24:30 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2020-06-26 08:24:44 -0700 |
| commit | 63112cd67b21c9ee1c1db903d6b13a6c30ce6dab (patch) | |
| tree | 718c03e59e830ee08235d04b55e633f33e055a61 /opcodes/i386-gen.c | |
| parent | 8e6635bd14a94d4363ad79f5bb40fcc7b99a2ca6 (diff) | |
| download | gdb-63112cd67b21c9ee1c1db903d6b13a6c30ce6dab.zip gdb-63112cd67b21c9ee1c1db903d6b13a6c30ce6dab.tar.gz gdb-63112cd67b21c9ee1c1db903d6b13a6c30ce6dab.tar.bz2 | |
x86: Rename VecSIB to SIB for Intel AMX
Rename VecSIB to SIB to support Intel Advanced Matrix Extensions which
introduces instructions with a mandatory SIB byte which isn't a vector
SIB (VSIB).
gas/
* config/tc-i386.c (check_VecOperands): Replace vecsib with sib.
Replace VecSIB128, VecSIB256 and VecSIB512 with VECSIB128,
VECSIB256 and VECSIB512, respectively.
(build_modrm_byte): Replace vecsib with sib.
opcodes/
* i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
(VecSIB128): Renamed to ...
(VECSIB128): This.
(VecSIB256): Renamed to ...
(VECSIB256): This.
(VecSIB512): Renamed to ...
(VECSIB512): This.
(VecSIB): Renamed to ...
(SIB): This.
(i386_opcode_modifier): Replace vecsib with sib.
* i386-opc.tbl (VexSIB128): New.
(VecSIB256): Likewise.
(VecSIB512): Likewise.
Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VexSIB128, VecSIB256
and VecSIB512, respectively.
Diffstat (limited to 'opcodes/i386-gen.c')
| -rw-r--r-- | opcodes/i386-gen.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 6e33fc5..e7454db 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -665,7 +665,7 @@ static bitfield opcode_modifiers[] = BITFIELD (VexW), BITFIELD (VexOpcode), BITFIELD (VexSources), - BITFIELD (VecSIB), + BITFIELD (SIB), BITFIELD (SSE2AVX), BITFIELD (NoAVX), BITFIELD (EVex), |