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| author | H.J. Lu <hjl.tools@gmail.com> | 2020-02-10 08:37:22 -0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2020-02-10 08:37:36 -0800 |
| commit | 4b5aaf5f6992319c2c72e080a1a55842640b8732 (patch) | |
| tree | b75a8c08300589ff7d3f6fb820be4d56fe8a1f54 /opcodes/i386-gen.c | |
| parent | 3a5d12fbb4f7888525978f9fba46b977afabe391 (diff) | |
| download | gdb-4b5aaf5f6992319c2c72e080a1a55842640b8732.zip gdb-4b5aaf5f6992319c2c72e080a1a55842640b8732.tar.gz gdb-4b5aaf5f6992319c2c72e080a1a55842640b8732.tar.bz2 | |
x86: Accept Intel64 only instruction by default
Commit d835a58baae720 disabled sysenter/sysenter in 64-bit mode by
default. By default, assembler should accept common, Intel64 only
and AMD64 ISAs since there are no conflicts.
gas/
PR gas/25516
* config/tc-i386.c (intel64): Renamed to ...
(isa64): This.
(match_template): Accept Intel64 only instruction by default.
(i386_displacement): Updated.
(md_parse_option): Updated.
* c-i386.texi: Update -mamd64/-mintel64 documentation.
* testsuite/gas/i386/i386.exp: Run x86-64-sysenter. Pass
-mamd64 to x86-64-sysenter-amd.
* testsuite/gas/i386/x86-64-sysenter.d: New file.
opcodes/
PR gas/25516
* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
with ISA64.
* i386-opc.h (AMD64): Removed.
(Intel64): Likewose.
(AMD64): New.
(INTEL64): Likewise.
(INTEL64ONLY): Likewise.
(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
* i386-opc.tbl (Amd64): New.
(Intel64): Likewise.
(Intel64Only): Likewise.
Replace AMD64 with Amd64. Update sysenter/sysenter with
Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-gen.c')
| -rw-r--r-- | opcodes/i386-gen.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 2784799..d7e29aa 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -666,8 +666,7 @@ static bitfield opcode_modifiers[] = BITFIELD (ATTMnemonic), BITFIELD (ATTSyntax), BITFIELD (IntelSyntax), - BITFIELD (AMD64), - BITFIELD (Intel64), + BITFIELD (ISA64), }; #define CLASS(n) #n, n |