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| author | H.J. Lu <hjl.tools@gmail.com> | 2008-01-04 01:05:45 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2008-01-04 01:05:45 +0000 |
| commit | 3629bb00a8c7689af995272018df56e85b82f569 (patch) | |
| tree | 0e6760bb541f4c2304edb948374eac8b7128c613 /opcodes/i386-gen.c | |
| parent | 2e5168804d07f991ed4266d2447f2525a7e2cfa0 (diff) | |
| download | gdb-3629bb00a8c7689af995272018df56e85b82f569.zip gdb-3629bb00a8c7689af995272018df56e85b82f569.tar.gz gdb-3629bb00a8c7689af995272018df56e85b82f569.tar.bz2 | |
gas/
2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/config/tc-i386.c (cpu_arch_flags_not): Removed.
(cpu_flags_not): Likewise.
(cpu_flags_match): Updated to check 64bit and arch.
(set_code_flag): Remove cpu_arch_flags_not.
(set_16bit_gcc_code_flag): Likewise.
(set_cpu_arch): Likewise.
(md_begin): Likewise.
(parse_insn): Call cpu_flags_match to check 64bit and arch.
(match_template): Likewise.
gas/testsuite/
2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-9.d: New file.
* gas/i386/arch-9.s: Likewise.
* gas/i386/i386.exp: Run arch-9.
opcodes/
2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
CpuSSE4_2_Or_ABM.
(cpu_flags): Likewise.
* i386-opc.h (CpuSSE4_1_Or_5): Removed.
(CpuSSE4_2_Or_ABM): Likewise.
(CpuLM): Updated.
(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
and CpuPadLock, respectively.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
Diffstat (limited to 'opcodes/i386-gen.c')
| -rw-r--r-- | opcodes/i386-gen.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 4b89fb2..1c79fae 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -81,7 +81,7 @@ static initializer cpu_flag_init [] = { "CPU_K8_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuLM" }, { "CPU_AMDFAM10_FLAGS", - "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE4_2_Or_ABM|CpuLM" }, + "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuK8|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuLM" }, { "CPU_MMX_FLAGS", "CpuMMX" }, { "CPU_SSE_FLAGS", @@ -93,9 +93,9 @@ static initializer cpu_flag_init [] = { "CPU_SSSE3_FLAGS", "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3" }, { "CPU_SSE4_1_FLAGS", - "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_1_Or_5" }, + "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1" }, { "CPU_SSE4_2_FLAGS", - "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuSSE4_1_Or_5|CpuSSE4_2_Or_ABM" }, + "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2" }, { "CPU_3DNOW_FLAGS", "CpuMMX|Cpu3dnow" }, { "CPU_3DNOWA_FLAGS", @@ -107,9 +107,9 @@ static initializer cpu_flag_init [] = { "CPU_SSE4A_FLAGS", "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a" }, { "CPU_ABM_FLAGS", - "CpuABM|CpuSSE4_2_Or_ABM" }, + "CpuABM" }, { "CPU_SSE5_FLAGS", - "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE5|CpuSSE4_1_Or_5|CpuSSE4_2_Or_ABM"}, + "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM|CpuSSE5"}, }; static initializer operand_type_init [] = @@ -234,8 +234,6 @@ static bitfield cpu_flags[] = BITFIELD (CpuSSE4_2), BITFIELD (CpuSSE4a), BITFIELD (CpuSSE5), - BITFIELD (CpuSSE4_1_Or_5), - BITFIELD (CpuSSE4_2_Or_ABM), BITFIELD (Cpu3dnow), BITFIELD (Cpu3dnowA), BITFIELD (CpuPadLock), |