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authorH.J. Lu <hjl.tools@gmail.com>2012-02-08 18:20:41 +0000
committerH.J. Lu <hjl.tools@gmail.com>2012-02-08 18:20:41 +0000
commit42164a7195927ffea7ad125ae132226c2fdec512 (patch)
tree97364b4ec2e7c7cef5eded0a0c88077469a678e3 /opcodes/i386-gen.c
parentc71bb1cf63afec7dd2303fd698c33b887441d1c8 (diff)
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Implement Intel Transactional Synchronization Extensions
gas/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (HLE_PREFIX): New. (check_hle): Likewise. (_i386_insn): Add have_hle. (cpu_arch): Add .hle and .rtm. (md_assemble): Call check_hle if i.have_hle isn't zero. (parse_insn): Set i.have_hle to 1 for HLE prefix. (output_jump): Support up to 2 byte opcode. * doc/c-i386.texi: Document hle/.hle and rtm/.rtm. gas/testsuite/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/hle-intel.d: New. * gas/i386/hle.d: Likewise. * gas/i386/hle.s: Likewise. * gas/i386/hlebad.l: Likewise. * gas/i386/hlebad.s: Likewise. * gas/i386/rtm-intel.d: Likewise. * gas/i386/rtm.d: Likewise. * gas/i386/rtm.s: Likewise. * gas/i386/x86-64-hle-intel.d: Likewise. * gas/i386/x86-64-hle.d: Likewise. * gas/i386/x86-64-hle.s: Likewise. * gas/i386/x86-64-hlebad.l: Likewise. * gas/i386/x86-64-hlebad.s: Likewise. * gas/i386/x86-64-rtm-intel.d: Likewise. * gas/i386/x86-64-rtm.d: Likewise. * gas/i386/x86-64-rtm.s: Likewise. * gas/i386/i386.exp: Run hle, hle-intel, hlebad x86-64-hle, rtm, rtm-intel, x86-64-hle-intel, x86-64-hlebad, x86-64-rtm and x86-64-rtm-intel. include/opcode/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * i386.h (XACQUIRE_PREFIX_OPCODE): New. (XRELEASE_PREFIX_OPCODE): Likewise. opcodes/ 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (HLE_Fixup1): New. (HLE_Fixup2): Likewise. (HLE_Fixup3): Likewise. (Ebh1): Likewise. (Evh1): Likewise. (Ebh2): Likewise. (Evh2): Likewise. (Ebh3): Likewise. (Evh3): Likewise. (MOD_C6_REG_7): Likewise. (MOD_C7_REG_7): Likewise. (RM_C6_REG_7): Likewise. (RM_C7_REG_7): Likewise. (XACQUIRE_PREFIX): Likewise. (XRELEASE_PREFIX): Likewise. (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov. (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg, not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use MOD_C6_REG_7 and MOD_C7_REG_7. (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7. (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and xtest. (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX. (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b. * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and CPU_RTM_FLAGS. (cpu_flags): Add CpuHLE and CpuRTM. (opcode_modifiers): Add HLEPrefixOk. * i386-opc.h (CpuHLE): New. (CpuRTM): Likewise. (HLEPrefixOk): Likewise. (i386_cpu_flags): Add cpuhle and cpurtm. (i386_opcode_modifier): Add hleprefixok. * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory operand. Add xacquire, xrelease, xabort, xbegin, xend and xtest. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.
Diffstat (limited to 'opcodes/i386-gen.c')
-rw-r--r--opcodes/i386-gen.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index ffdc7e6..21f600f 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -162,6 +162,10 @@ static initializer cpu_flag_init[] =
"CpuBMI2" },
{ "CPU_LZCNT_FLAGS",
"CpuLZCNT" },
+ { "CPU_HLE_FLAGS",
+ "CpuHLE" },
+ { "CPU_RTM_FLAGS",
+ "CpuRTM" },
{ "CPU_INVPCID_FLAGS",
"CpuINVPCID" },
{ "CPU_VMFUNC_FLAGS",
@@ -351,6 +355,8 @@ static bitfield cpu_flags[] =
BITFIELD (CpuF16C),
BITFIELD (CpuBMI2),
BITFIELD (CpuLZCNT),
+ BITFIELD (CpuHLE),
+ BITFIELD (CpuRTM),
BITFIELD (CpuINVPCID),
BITFIELD (CpuVMFUNC),
BITFIELD (Cpu64),
@@ -392,6 +398,7 @@ static bitfield opcode_modifiers[] =
BITFIELD (RegKludge),
BITFIELD (FirstXmm0),
BITFIELD (Implicit1stXmm0),
+ BITFIELD (HLEPrefixOk),
BITFIELD (ToDword),
BITFIELD (ToQword),
BITFIELD (AddrPrefixOp0),