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authorJan Beulich <jbeulich@suse.com>2020-02-13 10:19:28 +0100
committerJan Beulich <jbeulich@suse.com>2020-02-13 10:19:28 +0100
commit7deea9aad86683a4bcc68d6dd073038039f7a267 (patch)
tree5c65487902b62b9a4f48c25f47a30081f7408924 /opcodes/i386-gen.c
parentf3b0f7fe42309fa0e00b4d2074b0faefbf2e8ffd (diff)
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x86: fix SSE4a dependencies of ".arch .nosse*"
Since ".arch .sse4a" enables SSE3 and earlier, disabling SSE3 should also disable SSE4a. And as per its name, ".arch .nosse4" should also do so.
Diffstat (limited to 'opcodes/i386-gen.c')
-rw-r--r--opcodes/i386-gen.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index e1cc493..79f4cc9 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -322,17 +322,19 @@ static initializer cpu_flag_init[] =
{ "CPU_ANY_MMX_FLAGS",
"CPU_3DNOWA_FLAGS" },
{ "CPU_ANY_SSE_FLAGS",
- "CPU_ANY_SSE2_FLAGS|CpuSSE|CpuSSE4a" },
+ "CPU_ANY_SSE2_FLAGS|CpuSSE" },
{ "CPU_ANY_SSE2_FLAGS",
"CPU_ANY_SSE3_FLAGS|CpuSSE2" },
{ "CPU_ANY_SSE3_FLAGS",
- "CPU_ANY_SSSE3_FLAGS|CpuSSE3" },
+ "CPU_ANY_SSSE3_FLAGS|CpuSSE3|CpuSSE4a" },
{ "CPU_ANY_SSSE3_FLAGS",
"CPU_ANY_SSE4_1_FLAGS|CpuSSSE3" },
{ "CPU_ANY_SSE4_1_FLAGS",
"CPU_ANY_SSE4_2_FLAGS|CpuSSE4_1" },
{ "CPU_ANY_SSE4_2_FLAGS",
"CpuSSE4_2" },
+ { "CPU_ANY_SSE4_FLAGS",
+ "CPU_ANY_SSE4_1_FLAGS|CpuSSE4a" },
{ "CPU_ANY_AVX_FLAGS",
"CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" },
{ "CPU_ANY_AVX2_FLAGS",