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author | Jan Beulich <jbeulich@suse.com> | 2019-10-30 09:07:40 +0100 |
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committer | Jan Beulich <jbeulich@suse.com> | 2019-10-30 09:07:40 +0100 |
commit | 3cc17af5890d5877b8ac53eb5cd9a2adf82467e6 (patch) | |
tree | 2819878c197833e73797d9ae6408affd5a07be34 /opcodes/i386-gen.c | |
parent | a2cebd03faf935d292b524e999787d379a6b04ad (diff) | |
download | gdb-3cc17af5890d5877b8ac53eb5cd9a2adf82467e6.zip gdb-3cc17af5890d5877b8ac53eb5cd9a2adf82467e6.tar.gz gdb-3cc17af5890d5877b8ac53eb5cd9a2adf82467e6.tar.bz2 |
x86: re-do "shorthand" handling
Now that the opcode table gets preprocessed, undo parts of commit
dc821c5f9a ("x86: replace Reg8, Reg16, Reg32, and Reg64"): Have the
preprocessor handle the expansion there, while making the expansions
explicit in i386-gen and the register table.
Diffstat (limited to 'opcodes/i386-gen.c')
-rw-r--r-- | opcodes/i386-gen.c | 55 |
1 files changed, 13 insertions, 42 deletions
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index c48c675..a3160f2 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -379,31 +379,18 @@ static initializer cpu_flag_init[] = "CpuAVX512_VP2INTERSECT" }, }; -static const initializer operand_type_shorthands[] = -{ - { "Reg8", "Reg|Byte" }, - { "Reg16", "Reg|Word" }, - { "Reg32", "Reg|Dword" }, - { "Reg64", "Reg|Qword" }, - { "FloatAcc", "Acc|Tbyte" }, - { "FloatReg", "Reg|Tbyte" }, - { "RegXMM", "RegSIMD|Xmmword" }, - { "RegYMM", "RegSIMD|Ymmword" }, - { "RegZMM", "RegSIMD|Zmmword" }, -}; - static initializer operand_type_init[] = { { "OPERAND_TYPE_NONE", "0" }, { "OPERAND_TYPE_REG8", - "Reg8" }, + "Reg|Byte" }, { "OPERAND_TYPE_REG16", - "Reg16" }, + "Reg|Word" }, { "OPERAND_TYPE_REG32", - "Reg32" }, + "Reg|Dword" }, { "OPERAND_TYPE_REG64", - "Reg64" }, + "Reg|Qword" }, { "OPERAND_TYPE_IMM1", "Imm1" }, { "OPERAND_TYPE_IMM8", @@ -441,9 +428,9 @@ static initializer operand_type_init[] = { "OPERAND_TYPE_DEBUG", "Debug" }, { "OPERAND_TYPE_FLOATREG", - "FloatReg" }, + "Reg|Tbyte" }, { "OPERAND_TYPE_FLOATACC", - "FloatAcc" }, + "Acc|Tbyte" }, { "OPERAND_TYPE_SREG", "SReg" }, { "OPERAND_TYPE_JUMPABSOLUTE", @@ -451,11 +438,11 @@ static initializer operand_type_init[] = { "OPERAND_TYPE_REGMMX", "RegMMX" }, { "OPERAND_TYPE_REGXMM", - "RegXMM" }, + "RegSIMD|Xmmword" }, { "OPERAND_TYPE_REGYMM", - "RegYMM" }, + "RegSIMD|Ymmword" }, { "OPERAND_TYPE_REGZMM", - "RegZMM" }, + "RegSIMD|Zmmword" }, { "OPERAND_TYPE_REGMASK", "RegMask" }, { "OPERAND_TYPE_ESSEG", @@ -830,8 +817,8 @@ next_field (char *str, char sep, char **next, char *last) static void set_bitfield (char *, bitfield *, int, unsigned int, int); static int -set_bitfield_from_shorthand (char *f, bitfield *array, unsigned int size, - int lineno) +set_bitfield_from_cpu_flag_init (char *f, bitfield *array, unsigned int size, + int lineno) { char *str, *next, *last; unsigned int i; @@ -852,22 +839,6 @@ set_bitfield_from_shorthand (char *f, bitfield *array, unsigned int size, return 0; } - for (i = 0; i < ARRAY_SIZE (operand_type_shorthands); i++) - if (strcmp (operand_type_shorthands[i].name, f) == 0) - { - /* Turn on selective bits. */ - char *init = xstrdup (operand_type_shorthands[i].init); - last = init + strlen (init); - for (next = init; next && next < last; ) - { - str = next_field (next, '|', &next, last); - if (str) - set_bitfield (str, array, 1, size, lineno); - } - free (init); - return 0; - } - return -1; } @@ -918,8 +889,8 @@ set_bitfield (char *f, bitfield *array, int value, } } - /* Handle shorthands. */ - if (value == 1 && !set_bitfield_from_shorthand (f, array, size, lineno)) + /* Handle CPU_XXX_FLAGS. */ + if (value == 1 && !set_bitfield_from_cpu_flag_init (f, array, size, lineno)) return; if (lineno != -1) |