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| author | H.J. Lu <hjl.tools@gmail.com> | 2016-11-09 14:00:18 -0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2016-11-09 14:00:18 -0800 |
| commit | 60227d64dd9228be1a07fc7122894fc2875b1a70 (patch) | |
| tree | 23d17d6b4dd2732945be1cbe6699d39adf0263ea /opcodes/i386-dis.c | |
| parent | 1032d6ebdcd53b8c09c76a1c3b932065d84b0b20 (diff) | |
| download | gdb-60227d64dd9228be1a07fc7122894fc2875b1a70.zip gdb-60227d64dd9228be1a07fc7122894fc2875b1a70.tar.gz gdb-60227d64dd9228be1a07fc7122894fc2875b1a70.tar.bz2 | |
X86: Remove the .s suffix from EVEX vpextrw
The .s suffix indicates that the instruction is encoded by swapping
2 register operands. Since vpextrw takes an XMM register and an
integer register, the .s suffix should be ignored for EVEX vpextrw.
gas/
PR binutils/20799
* testsuite/gas/i386/opcode.s: Add a test for EVEX vpextrw.
* testsuite/gas/i386/opcode-intel.d: Updated.
* testsuite/gas/i386/opcode-suffix.d: Likewise.
* testsuite/gas/i386/opcode.d: Likewise.
* testsuite/gas/i386/x86-64-avx512bw-opts.s: Remove vpextrw
tests.
* testsuite/gas/i386/x86-64-avx512bw-opts-intel.d: Updated.
* testsuite/gas/i386/x86-64-avx512bw-opts.d: Likewise.
opcodes/
PR binutils/20799
* i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
* i386-dis.c (EdqwS): Removed.
(dqw_swap_mode): Likewise.
(intel_operand_size): Don't check dqw_swap_mode.
(OP_E_register): Likewise.
(OP_E_memory): Likewise.
(OP_G): Likewise.
(OP_EX): Likewise.
* i386-opc.tbl: Remove "S" from EVEX vpextrw.
* i386-tbl.h: Regerated.
Diffstat (limited to 'opcodes/i386-dis.c')
| -rw-r--r-- | opcodes/i386-dis.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index a15eabf..5f49f91 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -252,7 +252,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Ed { OP_E, d_mode } #define Edq { OP_E, dq_mode } #define Edqw { OP_E, dqw_mode } -#define EdqwS { OP_E, dqw_swap_mode } #define Edqb { OP_E, dqb_mode } #define Edb { OP_E, db_mode } #define Edw { OP_E, dw_mode } @@ -556,7 +555,6 @@ enum dq_mode, /* registers like dq_mode, memory like w_mode. */ dqw_mode, - dqw_swap_mode, bnd_mode, /* 4- or 6-byte pointer operand */ f_mode, @@ -14552,7 +14550,6 @@ intel_operand_size (int bytemode, int sizeflag) case w_mode: case dw_mode: case dqw_mode: - case dqw_swap_mode: oappend ("WORD PTR "); break; case indir_v_mode: @@ -14907,8 +14904,7 @@ OP_E_register (int bytemode, int sizeflag) if ((sizeflag & SUFFIX_ALWAYS) && (bytemode == b_swap_mode - || bytemode == v_swap_mode - || bytemode == dqw_swap_mode)) + || bytemode == v_swap_mode)) swap_operand (); switch (bytemode) @@ -14960,7 +14956,6 @@ OP_E_register (int bytemode, int sizeflag) case dqb_mode: case dqd_mode: case dqw_mode: - case dqw_swap_mode: USED_REX (REX_W); if (rex & REX_W) names = names64; @@ -15016,7 +15011,6 @@ OP_E_memory (int bytemode, int sizeflag) { case dqw_mode: case dw_mode: - case dqw_swap_mode: shift = 1; break; case dqb_mode: @@ -15490,7 +15484,6 @@ OP_G (int bytemode, int sizeflag) case dqb_mode: case dqd_mode: case dqw_mode: - case dqw_swap_mode: USED_REX (REX_W); if (rex & REX_W) oappend (names64[modrm.reg + add]); @@ -16345,7 +16338,6 @@ OP_EX (int bytemode, int sizeflag) if ((sizeflag & SUFFIX_ALWAYS) && (bytemode == x_swap_mode || bytemode == d_swap_mode - || bytemode == dqw_swap_mode || bytemode == d_scalar_swap_mode || bytemode == q_swap_mode || bytemode == q_scalar_swap_mode)) |