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| author | Igor Tsimbalist <igor.v.tsimbalist@intel.com> | 2017-10-20 22:52:59 +0300 |
|---|---|---|
| committer | Igor Tsimbalist <igor.v.tsimbalist@intel.com> | 2017-10-23 15:58:07 +0300 |
| commit | 53467f5707ec796c0490d55e74854258a78013f8 (patch) | |
| tree | da0d8ffc09bed88b35d42d7bc3acb00020a8b044 /opcodes/i386-dis.c | |
| parent | f6af9f3428fa86030ba8ecd2da7d11e4ee1ed989 (diff) | |
| download | gdb-53467f5707ec796c0490d55e74854258a78013f8.zip gdb-53467f5707ec796c0490d55e74854258a78013f8.tar.gz gdb-53467f5707ec796c0490d55e74854258a78013f8.tar.bz2 | |
Enable Intel AVX512_VBMI2 instructions.
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .avx512_vbmi2.
(cpu_noarch): noavx512_vbmi2.
* doc/c-i386.texi: Document .avx512_vbmi2, noavx512_vbmi2.
* testsuite/gas/i386/i386.exp: Add AVX512_VBMI2 tests.
* testsuite/gas/i386/avx512vbmi2-intel.d: New test.
* testsuite/gas/i386/avx512vbmi2.d: Likewise.
* testsuite/gas/i386/avx512vbmi2.s: Likewise.
* testsuite/gas/i386/avx512vbmi2_vl-intel.d: Likewise.
* testsuite/gas/i386/avx512vbmi2_vl.d: Likewise.
* testsuite/gas/i386/avx512vbmi2_vl.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2_vl-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2_vl.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vbmi2_vl.s: Likewise.
opcodes/
* i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
Define EXbScalar and EXwScalar for OP_EX.
(enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
(enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
(intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
(OP_E_memory): Likewise.
* i386-dis-evex.h: Updated.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
(cpu_flags): Add CpuAVX512_VBMI2.
* i386-opc.h (enum): Add CpuAVX512_VBMI2.
(i386_cpu_flags): Add cpuavx512_vbmi2.
* i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
Diffstat (limited to 'opcodes/i386-dis.c')
| -rw-r--r-- | opcodes/i386-dis.c | 34 |
1 files changed, 32 insertions, 2 deletions
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index edf5345..8d5bd27 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -376,7 +376,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define EMS { OP_EM, v_swap_mode } #define EMd { OP_EM, d_mode } #define EMx { OP_EM, x_mode } +#define EXbScalar { OP_EX, b_scalar_mode } #define EXw { OP_EX, w_mode } +#define EXwScalar { OP_EX, w_scalar_mode } #define EXd { OP_EX, d_mode } #define EXdScalar { OP_EX, d_scalar_mode } #define EXdS { OP_EX, d_swap_mode } @@ -598,6 +600,10 @@ enum /* scalar, ignore vector length. */ scalar_mode, + /* like b_mode, ignore vector length. */ + b_scalar_mode, + /* like w_mode, ignore vector length. */ + w_scalar_mode, /* like d_mode, ignore vector length. */ d_scalar_mode, /* like d_swap_mode, ignore vector length. */ @@ -1567,9 +1573,15 @@ enum PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, + PREFIX_EVEX_0F3862, + PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, + PREFIX_EVEX_0F3870, + PREFIX_EVEX_0F3871, + PREFIX_EVEX_0F3872, + PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, @@ -1685,7 +1697,11 @@ enum PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, - PREFIX_EVEX_0F3A67 + PREFIX_EVEX_0F3A67, + PREFIX_EVEX_0F3A70, + PREFIX_EVEX_0F3A71, + PREFIX_EVEX_0F3A72, + PREFIX_EVEX_0F3A73 }; enum @@ -2395,7 +2411,13 @@ enum EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, + EVEX_W_0F3862_P_2, + EVEX_W_0F3863_P_2, EVEX_W_0F3866_P_2, + EVEX_W_0F3870_P_2, + EVEX_W_0F3871_P_2, + EVEX_W_0F3872_P_2, + EVEX_W_0F3873_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, @@ -2443,7 +2465,11 @@ enum EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, - EVEX_W_0F3A67_P_2 + EVEX_W_0F3A67_P_2, + EVEX_W_0F3A70_P_2, + EVEX_W_0F3A71_P_2, + EVEX_W_0F3A72_P_2, + EVEX_W_0F3A73_P_2 }; typedef void (*op_rtn) (int bytemode, int sizeflag); @@ -14716,6 +14742,8 @@ intel_operand_size (int bytemode, int sizeflag) case x_swap_mode: case evex_x_gscat_mode: case evex_x_nobcst_mode: + case b_scalar_mode: + case w_scalar_mode: if (need_vex) { switch (vex.length) @@ -15168,9 +15196,11 @@ OP_E_memory (int bytemode, int sizeflag) case d_scalar_swap_mode: shift = 2; break; + case w_scalar_mode: case xmm_mw_mode: shift = 1; break; + case b_scalar_mode: case xmm_mb_mode: shift = 0; break; |