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| author | H.J. Lu <hjl.tools@gmail.com> | 2016-11-03 09:13:01 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2016-11-03 09:15:52 -0700 |
| commit | 8b89fe14b522cd6e5d160ff17defa8ecec243b11 (patch) | |
| tree | a9cd182a09e9fb3c0c8ecf3c269684633f98feed /opcodes/i386-dis.c | |
| parent | 722bcb33bf0383487c1af0e7d401e30301e94e2b (diff) | |
| download | gdb-8b89fe14b522cd6e5d160ff17defa8ecec243b11.zip gdb-8b89fe14b522cd6e5d160ff17defa8ecec243b11.tar.gz gdb-8b89fe14b522cd6e5d160ff17defa8ecec243b11.tar.bz2 | |
X86: Decode opcode 0x82 as opcode 0x80 in 32-bit mode
Update x86 disassembler to treat opcode 0x82 as an aliase of opcode 0x80
in 32-bit mode.
gas/
PR binutils/20754
* testsuite/gas/i386/opcode.s: Add tests for opcode 0x82.
* testsuite/gas/i386/opcode-intel.d: Updated.
* testsuite/gas/i386/opcode.d: Likewise.
opcodes/
PR binutils/20754
* i386-dis.c (REG_82): New.
(X86_64_82_REG_0): Likewise.
(X86_64_82_REG_1): Likewise.
(X86_64_82_REG_2): Likewise.
(X86_64_82_REG_3): Likewise.
(X86_64_82_REG_4): Likewise.
(X86_64_82_REG_5): Likewise.
(X86_64_82_REG_6): Likewise.
(X86_64_82_REG_7): Likewise.
(dis386): Use REG_82.
(reg_table): Add REG_82.
(x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
Diffstat (limited to 'opcodes/i386-dis.c')
| -rw-r--r-- | opcodes/i386-dis.c | 62 |
1 files changed, 61 insertions, 1 deletions
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 8fb607c..b0bb5e8 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -706,6 +706,7 @@ enum { REG_80 = 0, REG_81, + REG_82, REG_83, REG_8F, REG_C0, @@ -1694,6 +1695,14 @@ enum X86_64_63, X86_64_6D, X86_64_6F, + X86_64_82_REG_0, + X86_64_82_REG_1, + X86_64_82_REG_2, + X86_64_82_REG_3, + X86_64_82_REG_4, + X86_64_82_REG_5, + X86_64_82_REG_6, + X86_64_82_REG_7, X86_64_9A, X86_64_C4, X86_64_C5, @@ -2662,7 +2671,7 @@ static const struct dis386 dis386[] = { /* 80 */ { REG_TABLE (REG_80) }, { REG_TABLE (REG_81) }, - { Bad_Opcode }, + { REG_TABLE (REG_82) }, { REG_TABLE (REG_83) }, { "testB", { Eb, Gb }, 0 }, { "testS", { Ev, Gv }, 0 }, @@ -3400,6 +3409,17 @@ static const struct dis386 reg_table[][8] = { { "xorQ", { Evh1, Iv }, 0 }, { "cmpQ", { Ev, Iv }, 0 }, }, + /* REG_82 */ + { + { X86_64_TABLE (X86_64_82_REG_0) }, + { X86_64_TABLE (X86_64_82_REG_1) }, + { X86_64_TABLE (X86_64_82_REG_2) }, + { X86_64_TABLE (X86_64_82_REG_3) }, + { X86_64_TABLE (X86_64_82_REG_4) }, + { X86_64_TABLE (X86_64_82_REG_5) }, + { X86_64_TABLE (X86_64_82_REG_6) }, + { X86_64_TABLE (X86_64_82_REG_7) }, + }, /* REG_83 */ { { "addQ", { Evh1, sIb }, 0 }, @@ -6887,6 +6907,46 @@ static const struct dis386 x86_64_table[][2] = { { "outs{G|}", { indirDXr, Xz }, 0 }, }, + /* X86_64_82_REG_0 */ + { + { "addA", { Ebh1, Ib }, 0 }, + }, + + /* X86_64_82_REG_1 */ + { + { "orA", { Ebh1, Ib }, 0 }, + }, + + /* X86_64_82_REG_2 */ + { + { "adcA", { Ebh1, Ib }, 0 }, + }, + + /* X86_64_82_REG_3 */ + { + { "sbbA", { Ebh1, Ib }, 0 }, + }, + + /* X86_64_82_REG_4 */ + { + { "andA", { Ebh1, Ib }, 0 }, + }, + + /* X86_64_82_REG_5 */ + { + { "subA", { Ebh1, Ib }, 0 }, + }, + + /* X86_64_82_REG_6 */ + { + { "xorA", { Ebh1, Ib }, 0 }, + }, + + /* X86_64_82_REG_7 */ + { + { "cmpA", { Eb, Ib }, 0 }, + }, + /* X86_64_9A */ { { "Jcall{T|}", { Ap }, 0 }, |