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| author | Sudi Das <sudi.das@arm.com> | 2019-01-25 14:28:07 +0000 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2019-01-25 14:49:53 +0000 |
| commit | 69105ce4c42e5644ab92cb9b2765ff5ce6bf7b1b (patch) | |
| tree | 03e21bc1d88aa8a4cb469aa6d5ab4c7dc6ae3491 /opcodes/i386-dis.c | |
| parent | 20a4ca5524b9bde2f5dfb19661570c25a3b05e5d (diff) | |
| download | gdb-69105ce4c42e5644ab92cb9b2765ff5ce6bf7b1b.zip gdb-69105ce4c42e5644ab92cb9b2765ff5ce6bf7b1b.tar.gz gdb-69105ce4c42e5644ab92cb9b2765ff5ce6bf7b1b.tar.bz2 | |
AArch64: Update encodings for stg, st2g, stzg and st2zg.
This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch updates the st*g instructions
to use a previously reserved field for a new register operand. Thus the
new versions of the instructions are as follows:
- STG Xt, [<Xn|SP>, #<simm>]
- STG Xt, [<Xn|SP>, #<simm>]!
- STG Xt, [<Xn|SP>], #<simm>
- STZG Xt, [<Xn|SP>, #<simm>]
- STZG Xt, [<Xn|SP>, #<simm>]!
- STZG Xt, [<Xn|SP>], #<simm>
- ST2G Xt, [<Xn|SP>, #<simm>]
- ST2G Xt, [<Xn|SP>, #<simm>]!
- ST2G Xt, [<Xn|SP>], #<simm>
- STZ2G Xt, [<Xn|SP>, #<simm>]
- STZ2G Xt, [<Xn|SP>, #<simm>]!
- STZ2G Xt, [<Xn|SP>], #<simm>
Committed on behalf of Sudakshina Das.
*** gas/ChangeLog ***
* config/tc-aarch64.c (warn_unpredictable_ldst): Exempt
stg, st2g, stzg and stz2g from Xt == Xn with writeback warning.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Change tests for
stg, stzg, st2g and stz2g.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** opcodes/ChangeLog ***
* aarch64-tbl.h (QL_LDST_AT): Update macro.
(aarch64_opcode): Change encoding for stg, stzg
st2g and st2zg.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
Diffstat (limited to 'opcodes/i386-dis.c')
0 files changed, 0 insertions, 0 deletions