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| author | Jan Beulich <jbeulich@suse.com> | 2020-01-30 11:36:33 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2020-01-30 11:36:33 +0100 |
| commit | aeab2b26dbea33221db4debaf31c97277cfaea5e (patch) | |
| tree | ea035fa04bc87aab42f5381626f3a213273fc992 /opcodes/i386-dis.c | |
| parent | 873494c89fb44747c7514687da25fc163c791b84 (diff) | |
| download | gdb-aeab2b26dbea33221db4debaf31c97277cfaea5e.zip gdb-aeab2b26dbea33221db4debaf31c97277cfaea5e.tar.gz gdb-aeab2b26dbea33221db4debaf31c97277cfaea5e.tar.bz2 | |
x86-64: honor vendor specifics for near RET
While vendors agree about default operand size (64 bits) and hence
unavilability of a 32-bit form, AMD honors a 16-bit operand size
override (0x66) while Intel doesn't.
Diffstat (limited to 'opcodes/i386-dis.c')
| -rw-r--r-- | opcodes/i386-dis.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index e6f73bf..d3746b0 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1764,6 +1764,8 @@ enum X86_64_6F, X86_64_82, X86_64_9A, + X86_64_C2, + X86_64_C3, X86_64_C4, X86_64_C5, X86_64_CE, @@ -2586,8 +2588,8 @@ static const struct dis386 dis386[] = { /* c0 */ { REG_TABLE (REG_C0) }, { REG_TABLE (REG_C1) }, - { "retT", { Iw, BND }, 0 }, - { "retT", { BND }, 0 }, + { X86_64_TABLE (X86_64_C2) }, + { X86_64_TABLE (X86_64_C3) }, { X86_64_TABLE (X86_64_C4) }, { X86_64_TABLE (X86_64_C5) }, { REG_TABLE (REG_C6) }, @@ -6901,6 +6903,18 @@ static const struct dis386 x86_64_table[][2] = { { "Jcall{T|}", { Ap }, 0 }, }, + /* X86_64_C2 */ + { + { "retP", { Iw, BND }, 0 }, + { "ret@", { Iw, BND }, 0 }, + }, + + /* X86_64_C3 */ + { + { "retP", { BND }, 0 }, + { "ret@", { BND }, 0 }, + }, + /* X86_64_C4 */ { { MOD_TABLE (MOD_C4_32BIT) }, |