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| author | Jan Beulich <jbeulich@novell.com> | 2015-04-23 16:42:40 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2015-04-23 16:42:40 +0200 |
| commit | 04d824a468650c632d228b977006139f17d646a4 (patch) | |
| tree | 1fc66e25aab33ba9ef1109ec3d6a0ad7001539b2 /opcodes/i386-dis.c | |
| parent | af508cb92f8fa7eed6c7f2bd3a49d42701db5900 (diff) | |
| download | gdb-04d824a468650c632d228b977006139f17d646a4.zip gdb-04d824a468650c632d228b977006139f17d646a4.tar.gz gdb-04d824a468650c632d228b977006139f17d646a4.tar.bz2 | |
x86: disambiguate disassembly of certain AVX512 insns
Certain conversion operations as well as vfpclassp{d,s} are ambiguous
when the input operand is in memory and no broadcast is being used.
While in Intel mode this gets resolved by printing suitable operand
size modifiers, AT&T mode need mnemonic suffixes to be added.
gas/testsuite/
2015-04-23 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512dq.d: Add 'z' suffix to vfpclassp{d,s} non-
register, non-broadcast cases.
* gas/i386/x86-64-avx512dq.d: Likewise.
* gas/i386/avx512dq_vl.d: Add 'x' and 'y' suffixes to
vcvt{,u}qq2ps and vfpclassp{d,s} non-register, non-broadcast
cases.
* gas/i386/x86-64-avx512dq_vl.d: Likewise.
* gas/i386/avx512f_vl.d: Add 'x' and 'y' suffixes to
vcvt{,t}pd2{,u}dq and vcvtpd2ps non-register, non-broadcast
cases.
* gas/i386/x86-64-avx512f_vl.d: Likewise.
opcodes/
2015-04-23 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
(vfpclasspd, vfpclassps): Add %XZ.
Diffstat (limited to 'opcodes/i386-dis.c')
| -rw-r--r-- | opcodes/i386-dis.c | 40 |
1 files changed, 36 insertions, 4 deletions
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index a25acc6..88c1758 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -2413,8 +2413,10 @@ struct dis386 { '%' => add 1 upper case letter to the macro. 2 upper case letter macros: - "XY" => print 'x' or 'y' if no register operands or suffix_always - is true. + "XY" => print 'x' or 'y' if suffix_always is true or no register + operands and no broadcast. + "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no + register operands and no broadcast. "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand or suffix_always is true @@ -13795,6 +13797,34 @@ case_B: *obufp++ = 'd'; break; case 'Z': + if (l != 0 || len != 1) + { + if (l != 1 || len != 2 || last[0] != 'X') + { + SAVE_LAST (*p); + break; + } + if (!need_vex || !vex.evex) + abort (); + if (intel_syntax + || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) + break; + switch (vex.length) + { + case 128: + *obufp++ = 'x'; + break; + case 256: + *obufp++ = 'y'; + break; + case 512: + *obufp++ = 'z'; + break; + default: + abort (); + } + break; + } if (intel_syntax) break; if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) @@ -14093,7 +14123,7 @@ case_S: if (!need_vex) abort (); if (intel_syntax - || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) + || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) break; switch (vex.length) { @@ -14103,8 +14133,10 @@ case_S: case 256: *obufp++ = 'y'; break; + case 512: + if (!vex.evex) default: - abort (); + abort (); } } break; |