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| author | H.J. Lu <hjl.tools@gmail.com> | 2017-06-21 08:32:38 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2017-06-21 08:32:51 -0700 |
| commit | 2234eee61c42ad3f4d17894236873e04b633e969 (patch) | |
| tree | 2448caa5f0815f1bf07b5314e6315f32e24d13fb /opcodes/i386-dis.c | |
| parent | c2f7640243bdab93cafb3bf516e17a72fcc2f051 (diff) | |
| download | gdb-2234eee61c42ad3f4d17894236873e04b633e969.zip gdb-2234eee61c42ad3f4d17894236873e04b633e969.tar.gz gdb-2234eee61c42ad3f4d17894236873e04b633e969.tar.bz2 | |
x86: CET v2.0: Update incssp and setssbsy
Update x86 assembler and disassembler for CET v2.0:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
1. incsspd and incsspq are changed to take a register opeand with a
different opcode.
2. setssbsy is changed to take no opeand with a different opcode.
gas/
* testsuite/gas/i386/cet-intel.d: Updated.
* testsuite/gas/i386/cet.d: Likewise.
* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
* testsuite/gas/i386/x86-64-cet.d: Likewise.
* testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests.
* testsuite/gas/i386/x86-64-cet.s: Likewise.
opcodes/
* i386-dis.c (RM_0FAE_REG_5): Removed.
(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
(PREFIX_MOD_3_0F01_REG_5_RM_0): New.
(PREFIX_MOD_3_0FAE_REG_5): Likewise.
(prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
PREFIX_MOD_3_0F01_REG_5_RM_0.
(prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
PREFIX_MOD_3_0FAE_REG_5.
(mod_table): Update MOD_0FAE_REG_5.
(rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
* i386-opc.tbl: Update incsspd, incsspq and setssbsy.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-dis.c')
| -rw-r--r-- | opcodes/i386-dis.c | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 58d4c06..612e06f 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -940,7 +940,6 @@ enum RM_0F01_REG_5, RM_0F01_REG_7, RM_0F1E_MOD_3_REG_7, - RM_0FAE_REG_5, RM_0FAE_REG_6, RM_0FAE_REG_7 }; @@ -949,7 +948,7 @@ enum { PREFIX_90 = 0, PREFIX_MOD_0_0F01_REG_5, - PREFIX_MOD_3_0F01_REG_5_RM_1, + PREFIX_MOD_3_0F01_REG_5_RM_0, PREFIX_MOD_3_0F01_REG_5_RM_2, PREFIX_0F10, PREFIX_0F11, @@ -997,6 +996,7 @@ enum PREFIX_MOD_0_0FAE_REG_4, PREFIX_MOD_3_0FAE_REG_4, PREFIX_MOD_0_0FAE_REG_5, + PREFIX_MOD_3_0FAE_REG_5, PREFIX_0FAE_REG_6, PREFIX_0FAE_REG_7, PREFIX_0FB8, @@ -3789,10 +3789,10 @@ static const struct dis386 prefix_table[][4] = { { "rstorssp", { Mq }, PREFIX_OPCODE }, }, - /* PREFIX_MOD_3_0F01_REG_5_RM_1 */ + /* PREFIX_MOD_3_0F01_REG_5_RM_0 */ { { Bad_Opcode }, - { "incsspK", { Skip_MODRM }, PREFIX_OPCODE }, + { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, }, /* PREFIX_MOD_3_0F01_REG_5_RM_2 */ @@ -4134,7 +4134,12 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_MOD_0_0FAE_REG_5 */ { { "xrstor", { FXSAVE }, PREFIX_OPCODE }, - { "setssbsy", { Mq }, PREFIX_OPCODE }, + }, + + /* PREFIX_MOD_3_0FAE_REG_5 */ + { + { "lfence", { Skip_MODRM }, 0 }, + { "incsspK", { Rdq }, PREFIX_OPCODE }, }, /* PREFIX_0FAE_REG_6 */ @@ -11657,7 +11662,7 @@ static const struct dis386 mod_table[][2] = { { /* MOD_0FAE_REG_5 */ { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) }, - { RM_TABLE (RM_0FAE_REG_5) }, + { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) }, }, { /* MOD_0FAE_REG_6 */ @@ -12233,8 +12238,8 @@ static const struct dis386 rm_table[][8] = { }, { /* RM_0F01_REG_5 */ + { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_1) }, { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) }, { Bad_Opcode }, { Bad_Opcode }, @@ -12262,10 +12267,6 @@ static const struct dis386 rm_table[][8] = { { "nopQ", { Ev }, 0 }, }, { - /* RM_0FAE_REG_5 */ - { "lfence", { Skip_MODRM }, 0 }, - }, - { /* RM_0FAE_REG_6 */ { "mfence", { Skip_MODRM }, 0 }, }, |