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author | Igor Tsimbalist <igor.v.tsimbalist@intel.com> | 2017-10-20 23:42:40 +0300 |
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committer | Igor Tsimbalist <igor.v.tsimbalist@intel.com> | 2017-10-23 15:58:18 +0300 |
commit | ff1982d53a1fba573e7f9a3b455f7644440cb336 (patch) | |
tree | 0b68e46cb8d693c73dde19722009972f6939a7e2 /opcodes/i386-dis-evex.h | |
parent | 8dcf1fadf2b0763962639fc5dcedc1892e502265 (diff) | |
download | gdb-ff1982d53a1fba573e7f9a3b455f7644440cb336.zip gdb-ff1982d53a1fba573e7f9a3b455f7644440cb336.tar.gz gdb-ff1982d53a1fba573e7f9a3b455f7644440cb336.tar.bz2 |
Enable Intel VPCLMULQDQ instruction.
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add VPCLMULQDQ.
* doc/c-i386.texi: Document VPCLMULQDQ.
* testsuite/gas/i386/i386.exp: Run VPCLMULQDQ tests.
* testsuite/gas/i386/avx512f_vpclmulqdq-intel.d: New test.
* testsuite/gas/i386/avx512f_vpclmulqdq-wig.s: Ditto.
* testsuite/gas/i386/avx512f_vpclmulqdq-wig1-intel.d: Ditto.
* testsuite/gas/i386/avx512f_vpclmulqdq-wig1.d: Ditto.
* testsuite/gas/i386/avx512f_vpclmulqdq.d: Ditto.
* testsuite/gas/i386/avx512f_vpclmulqdq.s: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq-wig.s: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq.d: Ditto.
* testsuite/gas/i386/avx512vl_vpclmulqdq.s: Ditto.
* testsuite/gas/i386/vpclmulqdq-intel.d: Ditto.
* testsuite/gas/i386/vpclmulqdq.d: Ditto.
* testsuite/gas/i386/vpclmulqdq.s: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig.s: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq-wig1.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d: Ditto.
* testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig.s: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq-wig1.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.d: Ditto.
* testsuite/gas/i386/x86-64-avx512vl_vpclmulqdq.s: Ditto.
* testsuite/gas/i386/x86-64-vpclmulqdq-intel.d: Ditto.
* testsuite/gas/i386/x86-64-vpclmulqdq.d: Ditto.
* testsuite/gas/i386/x86-64-vpclmulqdq.s: Ditto.
opcodes/
* i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
(enum): Remove VEX_LEN_0F3A44_P_2.
(vex_len_table): Ditto.
(enum): Remove VEX_W_0F3A44_P_2.
(vew_w_table): Ditto.
(prefix_table): Adjust instructions (see prefixes above).
* i386-dis-evex.h (evex_table):
Add new instructions (see prefixes above).
* i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
(bitfield_cpu_flags): Ditto.
* i386-opc.h (enum): Ditto.
(i386_cpu_flags): Ditto.
(CpuUnused): Comment out to avoid zero-width field problem.
* i386-opc.tbl (vpclmulqdq): New instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Ditto.
Diffstat (limited to 'opcodes/i386-dis-evex.h')
-rw-r--r-- | opcodes/i386-dis-evex.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index e72c472..ef5c963 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -662,7 +662,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { PREFIX_TABLE (PREFIX_EVEX_0F3A42) }, { PREFIX_TABLE (PREFIX_EVEX_0F3A43) }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_0F3A44) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -2779,6 +2779,12 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { VEX_W_TABLE (EVEX_W_0F3A43_P_2) }, }, + /* PREFIX_EVEX_0F3A44 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "vpclmulqdq", { XM, Vex, EXx, Ib }, 0 }, + }, /* PREFIX_EVEX_0F3A50 */ { { Bad_Opcode }, |