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| author | Jan Beulich <jbeulich@suse.com> | 2022-01-14 10:54:21 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2022-01-14 10:54:21 +0100 |
| commit | 2235ecb8afebeb56baf29eb98de34cfa1b95f697 (patch) | |
| tree | f75c3ae08807157db4430a4f69b1643fa499339d /opcodes/i386-dis-evex-w.h | |
| parent | 62dd9d917793f475024ce35eeb323608dc9d3bde (diff) | |
| download | gdb-2235ecb8afebeb56baf29eb98de34cfa1b95f697.zip gdb-2235ecb8afebeb56baf29eb98de34cfa1b95f697.tar.gz gdb-2235ecb8afebeb56baf29eb98de34cfa1b95f697.tar.bz2 | |
x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[]
Like already indicated during review of the original submission, there's
really only very few insns where going through this table is easier /
cheaper than using suitable macros. Utilize %XH more and introduce
similar %XS and %XD (which subsequently can be used for further table
size reduction).
While there also switch to using oappend() in 'XH' macro processing.
Diffstat (limited to 'opcodes/i386-dis-evex-w.h')
| -rw-r--r-- | opcodes/i386-dis-evex-w.h | 63 |
1 files changed, 3 insertions, 60 deletions
diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h index 62c3d3b..fc0a079 100644 --- a/opcodes/i386-dis-evex-w.h +++ b/opcodes/i386-dis-evex-w.h @@ -550,19 +550,11 @@ { Bad_Opcode }, { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA }, }, - /* EVEX_W_0F3A08 */ - { - { PREFIX_TABLE (PREFIX_EVEX_0F3A08_W_0) }, - }, /* EVEX_W_0F3A09 */ { { Bad_Opcode }, { "vrndscalepd", { XM, EXx, EXxEVexS, Ib }, PREFIX_DATA }, }, - /* EVEX_W_0F3A0A */ - { - { PREFIX_TABLE (PREFIX_EVEX_0F3A0A_W_0) }, - }, /* EVEX_W_0F3A0B */ { { Bad_Opcode }, @@ -636,62 +628,13 @@ { Bad_Opcode }, { "vpshrdw", { XM, Vex, EXx, Ib }, 0 }, }, - /* EVEX_W_MAP5_5A */ - { - { PREFIX_TABLE (PREFIX_EVEX_MAP5_5A_W_0) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_5A_W_1) }, - }, - /* EVEX_W_MAP5_5B */ - { - { PREFIX_TABLE (PREFIX_EVEX_MAP5_5B_W_0) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_5B_W_1) }, - }, - /* EVEX_W_MAP5_78_P_0 */ - { - { "vcvttph2udq", { XM, EXxmmqh, EXxEVexS }, 0 }, - }, - /* EVEX_W_MAP5_78_P_2 */ - { - { "vcvttph2uqq", { XM, EXxmmqdh, EXxEVexS }, 0 }, - }, - /* EVEX_W_MAP5_79_P_0 */ - { - { "vcvtph2udq", { XM, EXxmmqh, EXxEVexR }, 0 }, - }, - /* EVEX_W_MAP5_79_P_2 */ + /* EVEX_W_MAP5_5B_P_0 */ { - { "vcvtph2uqq", { XM, EXxmmqdh, EXxEVexR }, 0 }, - }, - /* EVEX_W_MAP5_7A_P_2 */ - { - { "vcvttph2qq", { XM, EXxmmqdh, EXxEVexS }, 0 }, + { "vcvtdq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 }, + { "vcvtqq2ph%XZ", { XMM, EXx, EXxEVexR }, 0 }, }, /* EVEX_W_MAP5_7A_P_3 */ { { "vcvtudq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 }, { "vcvtuqq2ph%XZ", { XMM, EXx, EXxEVexR }, 0 }, }, - /* EVEX_W_MAP5_7B_P_2 */ - { - { "vcvtph2qq", { XM, EXxmmqdh, EXxEVexR }, 0 }, - }, - /* EVEX_W_MAP5_7C_P_0 */ - { - { "vcvttph2uw", { XM, EXxh, EXxEVexS }, 0 }, - }, - /* EVEX_W_MAP5_7C_P_2 */ - { - { "vcvttph2w", { XM, EXxh, EXxEVexS }, 0 }, - }, - /* EVEX_W_MAP5_7D */ - { - { PREFIX_TABLE (PREFIX_EVEX_MAP5_7D_W_0) }, - }, - /* EVEX_W_MAP6_13_P_0 */ - { - { "vcvtsh2ss", { XMM, VexScalar, EXw, EXxEVexS }, 0 }, - }, - /* EVEX_W_MAP6_13_P_2 */ - { - { "vcvtph2psx", { XM, EXxmmqh, EXxEVexS }, 0 }, - }, |