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| author | Doug Evans <dje@google.com> | 2010-01-06 05:30:19 +0000 |
|---|---|---|
| committer | Doug Evans <dje@google.com> | 2010-01-06 05:30:19 +0000 |
| commit | fe8afbc48fd3fba73600670fd2b0fcbfd45c440a (patch) | |
| tree | c9237754fd594908f3f099468e86daa793096487 /opcodes/frv-ibld.c | |
| parent | 7c5b2b7a2509d8cdf94a59cbbb44c13cbe6c6183 (diff) | |
| download | gdb-fe8afbc48fd3fba73600670fd2b0fcbfd45c440a.zip gdb-fe8afbc48fd3fba73600670fd2b0fcbfd45c440a.tar.gz gdb-fe8afbc48fd3fba73600670fd2b0fcbfd45c440a.tar.bz2 | |
cpu/
* m32c.cpu (f-dsp-32-u24): Fix mode of extract handler.
(f-dsp-40-u20, f-dsp-40-u24): Ditto.
opcodes/
* cgen-ibld.in: #include "cgen/basic-modes.h".
* fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
* lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
* mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
* xstormy16-ibld.c: Regenerate.
Diffstat (limited to 'opcodes/frv-ibld.c')
| -rw-r--r-- | opcodes/frv-ibld.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/opcodes/frv-ibld.c b/opcodes/frv-ibld.c index 07e5ce0..d628fd4 100644 --- a/opcodes/frv-ibld.c +++ b/opcodes/frv-ibld.c @@ -33,6 +33,7 @@ #include "symcat.h" #include "frv-desc.h" #include "frv-opc.h" +#include "cgen/basic-modes.h" #include "opintl.h" #include "safe-ctype.h" @@ -755,15 +756,15 @@ frv_cgen_insert_operand (CGEN_CPU_DESC cd, case FRV_OPERAND_LABEL16 : { long value = fields->f_label16; - value = ((int) (((value) - (pc))) >> (2)); + value = ((SI) (((value) - (pc))) >> (2)); errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 16, 32, total_length, buffer); } break; case FRV_OPERAND_LABEL24 : { { - FLD (f_labelH6) = ((int) (((FLD (f_label24)) - (pc))) >> (20)); - FLD (f_labelL18) = ((((unsigned int) (((FLD (f_label24)) - (pc))) >> (2))) & (262143)); + FLD (f_labelH6) = ((SI) (((FLD (f_label24)) - (pc))) >> (20)); + FLD (f_labelL18) = ((((UINT) (((FLD (f_label24)) - (pc))) >> (2))) & (262143)); } errmsg = insert_normal (cd, fields->f_labelH6, 0|(1<<CGEN_IFLD_SIGNED), 0, 30, 6, 32, total_length, buffer); if (errmsg) @@ -809,7 +810,7 @@ frv_cgen_insert_operand (CGEN_CPU_DESC cd, case FRV_OPERAND_SPR : { { - FLD (f_spr_h) = ((unsigned int) (FLD (f_spr)) >> (6)); + FLD (f_spr_h) = ((UINT) (FLD (f_spr)) >> (6)); FLD (f_spr_l) = ((FLD (f_spr)) & (63)); } errmsg = insert_normal (cd, fields->f_spr_h, 0, 0, 30, 6, 32, total_length, buffer); @@ -823,7 +824,7 @@ frv_cgen_insert_operand (CGEN_CPU_DESC cd, case FRV_OPERAND_U12 : { { - FLD (f_u12_h) = ((int) (FLD (f_u12)) >> (6)); + FLD (f_u12_h) = ((SI) (FLD (f_u12)) >> (6)); FLD (f_u12_l) = ((FLD (f_u12)) & (63)); } errmsg = insert_normal (cd, fields->f_u12_h, 0|(1<<CGEN_IFLD_SIGNED), 0, 17, 6, 32, total_length, buffer); |