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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2004-03-01 09:42:33 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2004-03-01 09:42:33 +0000 |
| commit | c7a48b9ac9215f67421a769c2986b6eb2a69780b (patch) | |
| tree | 7b7c194a858c08b0cbf6bff28a4689eda00f46a3 /opcodes/frv-desc.c | |
| parent | 8b73069fed6ec6b73e35eccdf186887d89ecb84b (diff) | |
| download | gdb-c7a48b9ac9215f67421a769c2986b6eb2a69780b.zip gdb-c7a48b9ac9215f67421a769c2986b6eb2a69780b.tar.gz gdb-c7a48b9ac9215f67421a769c2986b6eb2a69780b.tar.bz2 | |
cpu/
* frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
(scutss): Change unit to I0.
(calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
(mqsaths): Fix FR400-MAJOR categorization.
(media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
(media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
* frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
combinations.
opcodes/
* frv-desc.c, frv-opc.c: Regenerate.
sim/frv/
* cache.c (frv_cache_init): Change fr400 cache statistics to match
the fr405.
(non_cache_access): Add missing breaks.
* interrupts.c (set_exception_status_registers): Always set EAR15
for data_access_errors.
* memory.c (fr400_check_write_address): Remove redundant alignment
check.
* model.c: Regenerate.
Diffstat (limited to 'opcodes/frv-desc.c')
| -rw-r--r-- | opcodes/frv-desc.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/opcodes/frv-desc.c b/opcodes/frv-desc.c index f7eebfc..0835361 100644 --- a/opcodes/frv-desc.c +++ b/opcodes/frv-desc.c @@ -2433,7 +2433,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* scutss$pack $GRj,$GRk */ { FRV_INSN_SCUTSS, "scutss", "scutss", 32, - { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } + { 0, { (1<<MACH_FR400), UNIT_I0, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } }, /* scan$pack $GRi,$GRj,$GRk */ { @@ -4128,7 +4128,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* calll$pack @($GRi,$GRj) */ { FRV_INSN_CALLL, "calll", "calll", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_NONE } } + { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } } }, /* jmpil$pack @($GRi,$s12) */ { @@ -4138,7 +4138,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* callil$pack @($GRi,$s12) */ { FRV_INSN_CALLIL, "callil", "callil", 32, - { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_NONE } } + { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } } }, /* call$pack $label24 */ { @@ -4863,7 +4863,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* ccalll$pack @($GRi,$GRj),$CCi,$cond */ { FRV_INSN_CCALLL, "ccalll", "ccalll", 32, - { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_NONE } } + { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } } }, /* ici$pack @($GRi,$GRj) */ { @@ -5578,7 +5578,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } } + { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } } }, /* msathu$pack $FRinti,$FRintj,$FRintk */ { @@ -5823,17 +5823,17 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = /* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } } + { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } } }, /* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } } + { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } } }, /* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32, - { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } } + { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } } }, /* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ { |