Thu Nov 19 16:02:46 1998 Dave Brolley <brolley@cygnus.com>

	* fr30-opc.c: Regenerated.
	* fr30-opc.h: Regenerated.
	* fr30-dis.c: Regenerated.
	* fr30-asm.c: Regenerated.

1 files changed, 38 insertions, 17 deletions

diff --git a/opcodes/fr30-opc.h b/opcodes/fr30-opc.h
index 61b5f2d..0eb8b1a 100644
--- a/opcodes/fr30-opc.h
+++ b/opcodes/fr30-opc.h
@@ -107,6 +107,14 @@ typedef enum h_gr {
  , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
 } H_GR;
 
+/* Enum declaration for coprocessor registers.  */
+typedef enum h_cr {
+  H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3
+ , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7
+ , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11
+ , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15
+} H_CR;
+
 /* Enum declaration for dedicated registers.  */
 typedef enum h_dr {
   H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
@@ -135,13 +143,15 @@ typedef enum h_r15 {
 
 /* Enum declaration for fr30 operand types.  */
 typedef enum cgen_operand_type {
-  FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RS1
+  FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
+ , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1
  , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
- , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_M4, FR30_OPERAND_U8
- , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
- , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
- , FR30_OPERAND_DIR8, FR30_OPERAND_DIR9, FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9
- , FR30_OPERAND_LABEL12, FR30_OPERAND_CC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT
+ , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_M4
+ , FR30_OPERAND_U8, FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8
+ , FR30_OPERAND_DISP9, FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10
+ , FR30_OPERAND_I32, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9, FR30_OPERAND_DIR10
+ , FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW, FR30_OPERAND_REGLIST_HI
+ , FR30_OPERAND_CC, FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT
  , FR30_OPERAND_ZBIT, FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT
  , FR30_OPERAND_MAX
 } CGEN_OPERAND_TYPE;
@@ -215,7 +225,7 @@ typedef enum cgen_insn_type {
  , FR30_INSN_STR14B, FR30_INSN_STR15, FR30_INSN_STR15GR, FR30_INSN_STR15DR
  , FR30_INSN_STR15PS, FR30_INSN_MOV, FR30_INSN_MOVDR, FR30_INSN_MOVPS
  , FR30_INSN_MOV2DR, FR30_INSN_MOV2PS, FR30_INSN_JMP, FR30_INSN_JMPD
- , FR30_INSN_CALL, FR30_INSN_CALLD, FR30_INSN_CALLR, FR30_INSN_CALLRD
+ , FR30_INSN_CALLR, FR30_INSN_CALLRD, FR30_INSN_CALL, FR30_INSN_CALLD
  , FR30_INSN_RET, FR30_INSN_RETD, FR30_INSN_INT, FR30_INSN_INTE
  , FR30_INSN_RETI, FR30_INSN_BRA, FR30_INSN_BNO, FR30_INSN_BEQ
  , FR30_INSN_BNE, FR30_INSN_BC, FR30_INSN_BNC, FR30_INSN_BN
@@ -225,13 +235,15 @@ typedef enum cgen_insn_type {
  , FR30_INSN_BNED, FR30_INSN_BCD, FR30_INSN_BNCD, FR30_INSN_BND
  , FR30_INSN_BPD, FR30_INSN_BVD, FR30_INSN_BNVD, FR30_INSN_BLTD
  , FR30_INSN_BGED, FR30_INSN_BLED, FR30_INSN_BGTD, FR30_INSN_BLSD
- , FR30_INSN_BHID, FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B
- , FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H, FR30_INSN_DMOVR13B, FR30_INSN_DMOV2R13PI
- , FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH
- , FR30_INSN_DMOVR13PIB, FR30_INSN_DMOV2R15PD, FR30_INSN_DMOVR15PI, FR30_INSN_LDRES
- , FR30_INSN_STRES, FR30_INSN_NOP, FR30_INSN_ANDCCR, FR30_INSN_ORCCR
+ , FR30_INSN_BHID, FR30_INSN_DMOVR13, FR30_INSN_DMOVR13H, FR30_INSN_DMOVR13B
+ , FR30_INSN_DMOVR13PI, FR30_INSN_DMOVR13PIH, FR30_INSN_DMOVR13PIB, FR30_INSN_DMOVR15PI
+ , FR30_INSN_DMOV2R13, FR30_INSN_DMOV2R13H, FR30_INSN_DMOV2R13B, FR30_INSN_DMOV2R13PI
+ , FR30_INSN_DMOV2R13PIH, FR30_INSN_DMOV2R13PIB, FR30_INSN_DMOV2R15PD, FR30_INSN_LDRES
+ , FR30_INSN_STRES, FR30_INSN_COPOP, FR30_INSN_COPLD, FR30_INSN_COPST
+ , FR30_INSN_COPSV, FR30_INSN_NOP, FR30_INSN_ANDCCR, FR30_INSN_ORCCR
  , FR30_INSN_STILM, FR30_INSN_ADDSP, FR30_INSN_EXTSB, FR30_INSN_EXTUB
- , FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_ENTER, FR30_INSN_LEAVE
+ , FR30_INSN_EXTSH, FR30_INSN_EXTUH, FR30_INSN_LDM0, FR30_INSN_LDM1
+ , FR30_INSN_STM0, FR30_INSN_STM1, FR30_INSN_ENTER, FR30_INSN_LEAVE
  , FR30_INSN_XCHB, FR30_INSN_MAX
 } CGEN_INSN_TYPE;
 
@@ -253,11 +265,17 @@ struct cgen_fields
   long f_op4;
   long f_op5;
   long f_cc;
+  long f_ccc;
   long f_Rj;
   long f_Ri;
   long f_Rs1;
   long f_Rs2;
+  long f_Rjc;
+  long f_Ric;
+  long f_CRj;
+  long f_CRi;
   long f_u4;
+  long f_u4c;
   long f_i4;
   long f_m4;
   long f_u8;
@@ -274,6 +292,8 @@ struct cgen_fields
   long f_dir9;
   long f_dir10;
   long f_rel12;
+  long f_reglist_hi;
+  long f_reglist_low;
   int length;
 };
 
@@ -285,10 +305,10 @@ extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];
 /* Enum declaration for fr30 hardware types.  */
 typedef enum hw_type {
   HW_H_PC, HW_H_MEMORY, HW_H_SINT, HW_H_UINT
- , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_DR
- , HW_H_PS, HW_H_R13, HW_H_R14, HW_H_R15
- , HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT, HW_H_CBIT
- , HW_H_IBIT, HW_H_SBIT, HW_MAX
+ , HW_H_ADDR, HW_H_IADDR, HW_H_GR, HW_H_CR
+ , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
+ , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
+ , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_MAX
 } HW_TYPE;
 
 #define MAX_HW ((int) HW_MAX)
@@ -296,6 +316,7 @@ typedef enum hw_type {
 /* Hardware decls.  */
 
 extern CGEN_KEYWORD fr30_cgen_opval_h_gr;
+extern CGEN_KEYWORD fr30_cgen_opval_h_cr;
 extern CGEN_KEYWORD fr30_cgen_opval_h_dr;
 extern CGEN_KEYWORD fr30_cgen_opval_h_ps;
 extern CGEN_KEYWORD fr30_cgen_opval_h_r13;