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authorAlan Modra <amodra@gmail.com>2019-12-10 23:02:37 +1030
committerAlan Modra <amodra@gmail.com>2019-12-11 11:38:04 +1030
commit0ef562a4b5da6bc1f16b2ea801b228acafd033d8 (patch)
tree4d87c16e9066d5947b56c349141008c063a76b6f /opcodes/cr16-dis.c
parent2fd2b153a3819d3ab6b9c4cf06943d498187714c (diff)
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ubsan: cr16: left shift cannot be represented in type 'int'
This was: unsigned long mask = SBM (instruction->match_bits); with #define SBM(offs) ((((1 << (32 - offs)) -1) << (offs))) Well, there are a couple of problems. Firstly, the expression uses int values (1 rather than 1u or 1ul) resulting in the ubsan error, and secondly, a zero offs will result in a 32-bit shift which is undefined if ints are only 32 bits. * cr16-dis.c (EXTRACT, SBM): Rewrite. (cr16_match_opcode): Delete duplicate bcond test.
Diffstat (limited to 'opcodes/cr16-dis.c')
-rw-r--r--opcodes/cr16-dis.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/opcodes/cr16-dis.c b/opcodes/cr16-dis.c
index 65cf91c..68fbe42 100644
--- a/opcodes/cr16-dis.c
+++ b/opcodes/cr16-dis.c
@@ -30,11 +30,11 @@
/* Extract 'n_bits' from 'a' starting from offset 'offs'. */
#define EXTRACT(a, offs, n_bits) \
- (n_bits == 32 ? (((a) >> (offs)) & 0xffffffffL) \
- : (((a) >> (offs)) & ((1 << (n_bits)) -1)))
+ (((a) >> (offs)) & ((1ul << ((n_bits) - 1) << 1) - 1))
-/* Set Bit Mask - a mask to set all bits starting from offset 'offs'. */
-#define SBM(offs) ((((1 << (32 - offs)) -1) << (offs)))
+/* Set Bit Mask - a mask to set all bits in a 32-bit word starting
+ from offset 'offs'. */
+#define SBM(offs) ((1ul << 31 << 1) - (1ul << (offs)))
typedef struct
{
@@ -329,9 +329,6 @@ cr16_match_opcode (void)
while (instruction >= cr16_instruction)
{
mask = build_mask ();
- /* Adjust mask for bcond with 32-bit size instruction */
- if ((IS_INSN_MNEMONIC("b") && instruction->size == 2))
- mask = 0xff0f0000;
if ((doubleWord & mask) == BIN (instruction->match,
instruction->match_bits))