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| author | Jose E. Marchesi <jose.marchesi@oracle.com> | 2019-07-19 15:35:43 +0200 |
|---|---|---|
| committer | Jose E. Marchesi <jose.marchesi@oracle.com> | 2019-07-19 15:35:43 +0200 |
| commit | 231097b03afffd0c5a2b520cd999dbcbe8d64eda (patch) | |
| tree | 33315b4833f4f64ec8e1a04b037f8ec848b21e92 /opcodes/bpf-desc.c | |
| parent | 1802aae8449a4d693ba1f4efb8a7917c2f20990b (diff) | |
| download | gdb-231097b03afffd0c5a2b520cd999dbcbe8d64eda.zip gdb-231097b03afffd0c5a2b520cd999dbcbe8d64eda.tar.gz gdb-231097b03afffd0c5a2b520cd999dbcbe8d64eda.tar.bz2 | |
cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassembler
This patch changes the eBPF CPU description to prefer the register
names %r0 and %r6 instead of %a and %ctx when disassembling. This
matches better with the current practice, vs. cBPF.
It also updates the GAS tests in order to reflect this change.
Tested in a x86_64 host.
cpu/ChangeLog:
2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of
%a and %ctx.
opcodes/ChangeLog:
2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf-desc.c: Regenerated.
gas/ChangeLog:
2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/bpf/alu.d: Use %r6 instead of %ctx.
* testsuite/gas/bpf/lddw-be.d: Likewise.
* testsuite/gas/bpf/lddw.d: Likewise.
* testsuite/gas/bpf/alu-be.d: Likewise.
* testsuite/gas/bpf/alu32.d: Likewise.
Diffstat (limited to 'opcodes/bpf-desc.c')
| -rw-r--r-- | opcodes/bpf-desc.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/opcodes/bpf-desc.c b/opcodes/bpf-desc.c index 18ded6e..90adfe6 100644 --- a/opcodes/bpf-desc.c +++ b/opcodes/bpf-desc.c @@ -133,19 +133,19 @@ static const CGEN_MACH bpf_cgen_mach_table[] = { static CGEN_KEYWORD_ENTRY bpf_cgen_opval_h_gpr_entries[] = { - { "%a", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 }, { "%r1", 1, {0, {{{0, 0}}}}, 0, 0 }, { "%r2", 2, {0, {{{0, 0}}}}, 0, 0 }, { "%r3", 3, {0, {{{0, 0}}}}, 0, 0 }, { "%r4", 4, {0, {{{0, 0}}}}, 0, 0 }, { "%r5", 5, {0, {{{0, 0}}}}, 0, 0 }, - { "%ctx", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 }, { "%r7", 7, {0, {{{0, 0}}}}, 0, 0 }, { "%r8", 8, {0, {{{0, 0}}}}, 0, 0 }, { "%r9", 9, {0, {{{0, 0}}}}, 0, 0 }, { "%fp", 10, {0, {{{0, 0}}}}, 0, 0 }, - { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 }, - { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 }, + { "%a", 0, {0, {{{0, 0}}}}, 0, 0 }, + { "%ctx", 6, {0, {{{0, 0}}}}, 0, 0 }, { "%r10", 10, {0, {{{0, 0}}}}, 0, 0 } }; |