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| author | Mike Frysinger <vapier@gentoo.org> | 2011-02-13 18:54:49 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-02-13 18:54:49 +0000 |
| commit | 4db663940931db273ab59affa3d2af4cfe1e29e7 (patch) | |
| tree | 94981e624e82a953aee0da9e1a9d62cd442527aa /opcodes/bfin-dis.c | |
| parent | 36f446111a0aba2bbd622ea73a2b5a9a363e5f5c (diff) | |
| download | gdb-4db663940931db273ab59affa3d2af4cfe1e29e7.zip gdb-4db663940931db273ab59affa3d2af4cfe1e29e7.tar.gz gdb-4db663940931db273ab59affa3d2af4cfe1e29e7.tar.bz2 | |
opcodes: blackfin: fix decoding of dsp mult insns
When assigning to a register half, the mac0 part of the mult insn
was not decoding properly. It would always show a full dreg instead
of the dreg low half.
Once we fix the disassembler, we have to update a few of the gas
tests as their previous expected output was incorrect.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'opcodes/bfin-dis.c')
| -rw-r--r-- | opcodes/bfin-dis.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c index e6901dc..e7646c9 100644 --- a/opcodes/bfin-dis.c +++ b/opcodes/bfin-dis.c @@ -3084,7 +3084,7 @@ decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf) if (w1) { - OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst)); + OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst)); OUTS (outf, " = "); decode_multfunc (h01, h11, src0, src1, outf); @@ -3099,7 +3099,7 @@ decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf) if (w0) { - OUTS (outf, dregs (dst)); + OUTS (outf, P ? dregs (dst) : dregs_lo (dst)); OUTS (outf, " = "); decode_multfunc (h00, h10, src0, src1, outf); } |