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| author | Renlin Li <renlin.li@arm.com> | 2016-02-24 13:55:30 +0000 |
|---|---|---|
| committer | Renlin Li <renlin.li@arm.com> | 2016-02-24 14:02:51 +0000 |
| commit | 3e309328e8d91e37f2f3cea15f8a686d3bdfa700 (patch) | |
| tree | 7355b5d4b1b3ab76217baa8e5f7279b5e07bbf27 /opcodes/arm-dis.c | |
| parent | 8afc7bea4018bf535902503c9a25dd4a96dfa3ca (diff) | |
| download | gdb-3e309328e8d91e37f2f3cea15f8a686d3bdfa700.zip gdb-3e309328e8d91e37f2f3cea15f8a686d3bdfa700.tar.gz gdb-3e309328e8d91e37f2f3cea15f8a686d3bdfa700.tar.bz2 | |
[OPCODES][ARM]Fix mask for a few coprocessor opcodes.
opcodes/
2016-02-24 Renlin Li <renlin.li@arm.com>
* arm-dis.c (coprocessor_opcodes): Fix mask for vsel, vmaxnm, vminnm,
vrint(mpna).
gas/
2016-02-24 Renlin Li <renlin.li@arm.com>
* testsuite/gas/arm/mask_1.d: New.
* testsuite/gas/arm/mask_1.s: New.
Diffstat (limited to 'opcodes/arm-dis.c')
| -rw-r--r-- | opcodes/arm-dis.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 4960140..6bffc6d 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -820,17 +820,17 @@ static const struct opcode32 coprocessor_opcodes[] = /* FP v5. */ {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, + 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, + 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"}, + 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"}, + 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"}, + 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"}, + 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), @@ -840,9 +840,9 @@ static const struct opcode32 coprocessor_opcodes[] = {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), 0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, + 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"}, {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8), - 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, + 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"}, /* Generic coprocessor instructions. */ {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" }, |