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| author | Jim Wilson <jim.wilson@linaro.org> | 2017-02-19 13:16:56 -0800 |
|---|---|---|
| committer | Jim Wilson <jim.wilson@linaro.org> | 2017-02-19 13:16:56 -0800 |
| commit | 2e7e5e28909bcffe2267b417f9cff0441b576fba (patch) | |
| tree | c2aac362b90239464de9622e1cbdecc7e58851f1 /opcodes/arm-dis.c | |
| parent | ceae703d41819c1f03e3250b6e6df64dc6e7d3ff (diff) | |
| download | gdb-2e7e5e28909bcffe2267b417f9cff0441b576fba.zip gdb-2e7e5e28909bcffe2267b417f9cff0441b576fba.tar.gz gdb-2e7e5e28909bcffe2267b417f9cff0441b576fba.tar.bz2 | |
Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv.
sim/aarch64/
* simulator.c (do_vec_ADDV): Mov val declaration inside each case,
with type set to input type size.
(do_vec_xtl): Change bias from 3 to 4 for byte case.
sim/testsuite/sim/aarch64/
* bit.s: Change cmp immediates to account for addv bug fix.
* cmtst.s, ldn_single.s, stn_single.s: Likewise.
* xtl.s: New.
Diffstat (limited to 'opcodes/arm-dis.c')
0 files changed, 0 insertions, 0 deletions