aboutsummaryrefslogtreecommitdiff
path: root/opcodes/arm-dis.c
diff options
context:
space:
mode:
authorNick Clifton <nickc@redhat.com>2009-12-09 08:38:04 +0000
committerNick Clifton <nickc@redhat.com>2009-12-09 08:38:04 +0000
commit07a28fab1145a0c0fa124b737d3956fbe5c43e5e (patch)
treed67c81bf9528f373e64edd395fb63874347e6924 /opcodes/arm-dis.c
parent8d099ae953697a81dd49fa135b72e731de2a8f70 (diff)
downloadgdb-07a28fab1145a0c0fa124b737d3956fbe5c43e5e.zip
gdb-07a28fab1145a0c0fa124b737d3956fbe5c43e5e.tar.gz
gdb-07a28fab1145a0c0fa124b737d3956fbe5c43e5e.tar.bz2
PR 10924
* arm-dis.c (print_insn_arm): Mark insns that use the PC in post-indexed addressing as unpredictable.
Diffstat (limited to 'opcodes/arm-dis.c')
-rw-r--r--opcodes/arm-dis.c16
1 files changed, 11 insertions, 5 deletions
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index a871d23..3bfad52 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2931,11 +2931,17 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
NEGATIVE_BIT_SET ? "-" : "",
arm_regnames[given & 0xf]);
- /* Writeback is automatically implied by post- addressing.
- Setting the W bit is unnecessary and ARM specify it as
- being unpredictable. */
- if (WRITEBACK_BIT_SET && ! allow_unpredictable)
- func (stream, UNPREDICTABLE_INSTRUCTION);
+ if (! allow_unpredictable)
+ {
+ /* Writeback is automatically implied by post- addressing.
+ Setting the W bit is unnecessary and ARM specify it as
+ being unpredictable. */
+ if (WRITEBACK_BIT_SET
+ /* Specifying the PC register as the post-indexed
+ registers is also unpredictable. */
+ || ((given & 0xf) == 0xf))
+ func (stream, UNPREDICTABLE_INSTRUCTION);
+ }
}
}
break;