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| author | Jiong Wang <jiong.wang@arm.com> | 2017-11-08 13:15:12 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2017-11-08 13:15:12 +0000 |
| commit | dec41383fff7116c9f66cdeca3105e968047a4e6 (patch) | |
| tree | b99323b823783fee1f4919216e048967e15f0ba7 /opcodes/arm-dis.c | |
| parent | 6e98b3428bdd0bf388c3c72eb205105926b15a64 (diff) | |
| download | gdb-dec41383fff7116c9f66cdeca3105e968047a4e6.zip gdb-dec41383fff7116c9f66cdeca3105e968047a4e6.tar.gz gdb-dec41383fff7116c9f66cdeca3105e968047a4e6.tar.bz2 | |
Adds command line support for Armv8.4-A, via the new command line option -march=armv8.4-a. Add support for "+dotprod" ARM feature (required for ARMv8.4-A). Add assembler and disassembler support for new FP16 instructions introduced in Armv8.4-A
gas * config/tc-arm.c (arm_extensions):
(arm_archs): New entry for "armv8.4-a".
Add FPU_ARCH_DOTPROD_NEON_VFP_ARMV8.
(arm_ext_v8_2): New variable.
(enum arm_reg_type): New enumeration REG_TYPE_NSD.
(reg_expected_msgs): New entry for REG_TYPE_NSD.
(parse_typed_reg_or_scalar): Handle REG_TYPE_NSD.
(parse_scalar): Support REG_TYPE_VFS.
(enum operand_parse_code): New enumerations OP_RNSD and OP_RNSD_RNSC.
(parse_operands): Handle OP_RNSD and OP_RNSD_RNSC.
(NEON_SHAPE_DEF): New entries for DHH and DHS.
(neon_scalar_for_fmac_fp16_long): New function to generate Rm encoding
for new FP16 instructions in ARMv8.2-A.
(do_neon_fmac_maybe_scalar_long): New function to encode new FP16
instructions in ARMv8.2-A.
(do_neon_vfmal): Wrapper function for vfmal.
(do_neon_vfmsl): Wrapper function for vfmsl.
(insns): New entries for vfmal and vfmsl.
* doc/c-arm.texi (-march): Document "armv8.4-a".
* testsuite/gas/arm/dotprod-mandatory.d: New test.
* testsuite/gas/arm/armv8_2-a-fp16.s: New test source.
* testsuite/gas/arm/armv8_2-a-fp16-illegal.s: New test source.
* testsuite/gas/arm/armv8_2-a-fp16.d: New test.
* testsuite/gas/arm/armv8_3-a-fp16.d: New test.
* testsuite/gas/arm/armv8_4-a-fp16.d: New test.
* testsuite/gas/arm/armv8_2-a-fp16-thumb2.d: New test.
* testsuite/gas/arm/armv8_2-a-fp16-illegal.d: New test.
* testsuite/gas/arm/armv8_2-a-fp16-illegal.l: New error file.
opcodes * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
FP16 instructions, including vfmal.f16 and vfmsl.f16.
include * opcode/arm.h (ARM_AEXT2_V8_4A): Include Dot Product feature.
(ARM_EXT2_V8_4A): New macro.
(ARM_AEXT2_V8_4A): Likewise.
(ARM_ARCH_V8_4A): Likewise.
Diffstat (limited to 'opcodes/arm-dis.c')
| -rw-r--r-- | opcodes/arm-dis.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 59a5978..d5a20cb 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -912,6 +912,24 @@ static const struct opcode32 coprocessor_opcodes[] = {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD), 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"}, + /* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), + 0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), + 0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), + 0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), + 0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), + 0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), + 0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), + 0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A), + 0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"}, + /* V5 coprocessor instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, |