Add assembler support for ARMv8-M Mainline

2015-12-24  Thomas Preud'homme  <thomas.preudhomme@arm.com>

bfd/
    (tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account
    for new TAG_CPU_ARCH_V4T_PLUS_V6_M value.  Deal with NULL values in
    comb array.

binutils/
    * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch
    value.
    (arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use
    value.

gas/
    * config/tc-arm.c (arm_ext_m): Include ARMv8-M.
    (arm_ext_v8m): New feature for ARMv8-M.
    (arm_ext_atomics): New feature for ARMv8 atomics.
    (do_tt): New encoding function for TT* instructions.
    (insns): Add new entries for ARMv8-M specific instructions and
    reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
    (arm_archs): Define armv8-m.main architecture.
    (cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
    clarify the ordering rule.
    (aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
    Tag_CPU_arch values for ARMv7e-M detection.  Add logic to keep setting
    Tag_CPU_arch to ARMv8-A for -march=all.  Also set Tag_CPU_arch_profile
    to 'A' if extension bit for atomic instructions is set, unless it is
    ARMv8-M.  Set Tag_THUMB_ISA_use to 3 for ARMv8-M.  Set Tag_DIV_use to 0
    for ARMv8-M Mainline.

gas/testsuite/
    * gas/arm/archv8m.s: New file.
    * gas/arm/archv8m-main.d: Likewise.
    * gas/arm/attr-march-armv8m.main.d: Likewise.
    * gas/arm/any-armv8m.s: Likewise.
    * gas/arm/any-armv8m.d: Likewise.

include/elf/
    * arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare.
    (MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN.
    (TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15.

include/opcode/
    * arm.h (ARM_EXT2_ATOMICS): New extension bit.
    (ARM_EXT2_V8M): Likewise.
    (ARM_EXT_V8): Adjust comment with regards to atomics and remove
    mention of legacy use for that bit.
    (ARM_AEXT2_V8_1A): New architecture extension bitfield.
    (ARM_AEXT2_V8_2A): Likewise.
    (ARM_AEXT_V8M_MAIN): Likewise.
    (ARM_AEXT2_V8M): Likewise.
    (ARM_ARCH_V8A): Use ARM_EXT2_ATOMICS for features in second bitfield.
    (ARM_ARCH_V8_1A): Likewise with ARM_AEXT2_V8_1A.
    (ARM_ARCH_V8_2A): Likewise with ARM_AEXT2_V8_2A.
    (ARM_ARCH_V8M_MAIN): New architecture feature bitfield.
    (ARM_ARCH_V8A_FP): Use ARM_EXT2_ATOMICS for features in second bitfield
    and reindent.
    (ARM_ARCH_V8A_SIMD): Likewise.
    (ARM_ARCH_V8A_CRYPTOV1): Likewise.
    (ARM_ARCH_V8_1A_FP): Use ARM_AEXT2_V8_1A to set second bitfield of
    feature bits.
    (ARM_ARCH_V8_1A_SIMD): Likewise.
    (ARM_ARCH_V8_1A_CRYPTOV1): Likewise.

opcodes/
    * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl,
    stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of
    ARM_EXT_V8.
    (thumb32_opcodes): Add entries for wide ARMv8-M instructions.

1 files changed, 18 insertions, 12 deletions

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 94fe304..34f0e62 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1581,33 +1581,33 @@ static const struct opcode32 arm_opcodes[] =
     0x0320f005, 0x0fffffff, "sevl"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
-  {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
+  {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
   /* CRC32 instructions.  */
   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
@@ -2524,6 +2524,12 @@ static const struct opcode16 thumb_opcodes[] =
    makes heavy use of special-case bit patterns.  */
 static const struct opcode32 thumb32_opcodes[] =
 {
+  /* V8-M instructions.  */
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
+    0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
+    0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
+
   /* V8 instructions.  */
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
     0xf3af8005, 0xffffffff, "sevl%c.w"},