diff options
| author | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2012-08-24 08:14:04 +0000 |
|---|---|---|
| committer | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2012-08-24 08:14:04 +0000 |
| commit | 48adcd8ed515c2a4960713fc4ff3f98930062069 (patch) | |
| tree | 9585c3cd9afbdcdae624644b823bbf18275d0649 /opcodes/arm-dis.c | |
| parent | 4f51b4bdbbae0b751bb093ebcf568e5808fc87c2 (diff) | |
| download | gdb-48adcd8ed515c2a4960713fc4ff3f98930062069.zip gdb-48adcd8ed515c2a4960713fc4ff3f98930062069.tar.gz gdb-48adcd8ed515c2a4960713fc4ff3f98930062069.tar.bz2 | |
* gas/config/tc-arm.c (NEON_ENC_TAB): Add sha3op entry.
(do_crypto_3op_1): New function.
(do_sha1c): Likewise.
(do_sha1p): Likewise.
(do_sha1m): Likewise.
(do_sha1su0): Likewise.
(do_sha256h): Likewise.
(do_sha256h2): Likewise.
(do_sha256su1): Likewise.
(insns): Add SHA 3 operand instructions.
* gas/testsuite/gas/arm/armv8-a+crypto.d: Update testcase.
* gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise.
* opcodes/arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
Diffstat (limited to 'opcodes/arm-dis.c')
| -rw-r--r-- | opcodes/arm-dis.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index c0a6479..97a96d1 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -625,6 +625,13 @@ static const struct opcode32 neon_opcodes[] = {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, /* Three registers of the same length. */ + {FPU_CRYPTO_EXT_ARMV8, 0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, + {FPU_CRYPTO_EXT_ARMV8, 0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"}, {FPU_NEON_EXT_ARMV8, 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, {FPU_NEON_EXT_ARMV8, 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |