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| author | Jiong Wang <jiong.wang@arm.com> | 2017-08-09 17:52:54 +0100 |
|---|---|---|
| committer | Jiong Wang <jiong.wang@arm.com> | 2017-08-09 17:52:54 +0100 |
| commit | cc4a945a2687184c7cd4a0572e02965829517408 (patch) | |
| tree | 571345ba14e0aa796cdf3ba2cd48a4515edc52f5 /opcodes/arm-dis.c | |
| parent | cd3af38d7b3e66117e7964b6fea45e57d47169ff (diff) | |
| download | gdb-cc4a945a2687184c7cd4a0572e02965829517408.zip gdb-cc4a945a2687184c7cd4a0572e02965829517408.tar.gz gdb-cc4a945a2687184c7cd4a0572e02965829517408.tar.bz2 | |
[ARM] Don't warn on REG_SP when used in CRC32 instructions
According to ARMv8-A architecture manual, REG_SP is allowed in CRC32
instructions in Thumb mode. It is REG_PC that will cause unpredictable
behaviours on both ARM and Thumb.
This patch removes the incorrect warning on Thumb mode.
Meanwhile the disassembler is updated to use format "<bitfield>R" instead of
"<bitfield>S". "<bitfield>S" is not used elsewhere. so I have deleted related
code from the disassembler.
gas/
* config/tc-arm.c (do_crc32_1): Remove warning on REG_SP for thumb_mode.
* testsuite/gas/arm/crc32-armv8-a-bad.d: Update exepcted result.
* testsuite/gas/arm/crc32-armv8-r-bad.d: Likewise.
* testsuite/gas/arm/crc32-armv8-a.d: Likewise.
* testsuite/gas/arm/crc32-armv8-r.d: Likewise.
* testsuite/gas/arm/crc32-armv8-ar-bad.s: Update test case.
* testsuite/gas/arm/crc32-armv8-ar.s: Likewise.
* testsuite/gas/arm/crc32-bad.l: Update expected error message.
opcode/
* arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
register operands in CRC instructions.
(print_insn_thumb32): Remove "<bitfield>S" support. Updated the
comments.
Diffstat (limited to 'opcodes/arm-dis.c')
| -rw-r--r-- | opcodes/arm-dis.c | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 2500004..59a5978 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -2699,7 +2699,6 @@ static const struct opcode16 thumb_opcodes[] = %<bitfield>W print bitfield*4 in decimal %<bitfield>r print bitfield as an ARM register %<bitfield>R as %<>r but r15 is UNPREDICTABLE - %<bitfield>S as %<>R but r13 is UNPREDICTABLE %<bitfield>c print bitfield as a condition code %<bitfield>'c print specified char iff bitfield is all ones @@ -2767,17 +2766,17 @@ static const struct opcode32 thumb32_opcodes[] = /* CRC32 instructions. */ {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"}, + 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"}, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"}, + 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"}, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"}, + 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"}, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"}, + 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"}, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"}, + 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"}, {ARM_FEATURE_COPROC (CRC_EXT_ARMV8), - 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"}, + 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"}, /* V7 instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"}, @@ -5987,10 +5986,6 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) value_in_comment = val * 4; break; - case 'S': - if (val == 13) - is_unpredictable = TRUE; - /* Fall through. */ case 'R': if (val == 15) is_unpredictable = TRUE; |