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authorJim Wilson <wilson@tuliptree.org>2005-07-07 19:27:52 +0000
committerJim Wilson <wilson@tuliptree.org>2005-07-07 19:27:52 +0000
commit0fd3a4776c8f607cc778cde80f9215089d36387e (patch)
tree0332cbbb13c41fc1834d3e17001dfd97936c7c81 /opcodes/arm-dis.c
parent9968d831f9298e2dc60de7a77013c7b173441951 (diff)
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Kaveh Ghazi's printf format attribute checking patch.
bfd: * elf32-xtensa.c (vsprint_msg): Add format attribute. Fix format bugs. * vms.h (_bfd_vms_debug): Add format attribute. (_bfd_vms_debug, _bfd_hexdump): Fix typos. binutils: * bucomm.h (report): Add format attribute. * dlltool.c (inform): Likewise. * dllwrap.c (display, inform, warn): Likewise. * objdump.c (objdump_sprintf): Likewise. * readelf.c (error, warn): Likewise. Fix format bugs. gas: * config/tc-tic30.c (debug): Add format attribute. Fix format bugs. include: * dis-asm.h (fprintf_ftype): Add format attribute. opcodes: * arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c, d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c, ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c, m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c, ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c, v850-dis.c: Fix format bugs. * ia64-gen.c (fail, warn): Add format attribute. * or32-opc.c (debug): Likewise.
Diffstat (limited to 'opcodes/arm-dis.c')
-rw-r--r--opcodes/arm-dis.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index faff3a0..0f3b65e 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -1578,7 +1578,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
- func (stream, "%d", reg);
+ func (stream, "%ld", reg);
}
break;
case 'W':
@@ -1588,7 +1588,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
- func (stream, "%d", reg + 1);
+ func (stream, "%ld", reg + 1);
}
break;
case 'x':
@@ -1598,7 +1598,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
- func (stream, "0x%08x", reg);
+ func (stream, "0x%08lx", reg);
/* Some SWI instructions have special
meanings. */
@@ -1615,7 +1615,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
- func (stream, "%01x", reg & 0xf);
+ func (stream, "%01lx", reg & 0xf);
}
break;
case 'f':
@@ -1629,7 +1629,7 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
func (stream, "#%s",
arm_fp_const[reg & 7]);
else
- func (stream, "f%d", reg);
+ func (stream, "f%ld", reg);
}
break;
@@ -1991,7 +1991,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
long imm = (given & 0x07c0) >> 6;
if (imm == 0)
imm = 32;
- func (stream, "#%d", imm);
+ func (stream, "#%ld", imm);
}
break;
@@ -2024,15 +2024,15 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
break;
case 'd':
- func (stream, "%d", reg);
+ func (stream, "%ld", reg);
break;
case 'H':
- func (stream, "%d", reg << 1);
+ func (stream, "%ld", reg << 1);
break;
case 'W':
- func (stream, "%d", reg << 2);
+ func (stream, "%ld", reg << 2);
break;
case 'a':
@@ -2044,7 +2044,7 @@ print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
break;
case 'x':
- func (stream, "0x%04x", reg);
+ func (stream, "0x%04lx", reg);
break;
case 'B':