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| author | Cupertino Miranda <cmiranda@synopsys.com> | 2016-09-21 12:07:46 +0100 |
|---|---|---|
| committer | Cupertino Miranda <cmiranda@synopsys.com> | 2016-10-17 15:27:51 +0200 |
| commit | decf5bd1570be3de10aeab99869a9548d17b1354 (patch) | |
| tree | bfa93eba732168b5eabd9e309334d576328ead4b /opcodes/arc-tbl.h | |
| parent | 6d91379408b87b6d0c1cd4bc2880b530cc4ec721 (diff) | |
| download | gdb-decf5bd1570be3de10aeab99869a9548d17b1354.zip gdb-decf5bd1570be3de10aeab99869a9548d17b1354.tar.gz gdb-decf5bd1570be3de10aeab99869a9548d17b1354.tar.bz2 | |
Removed pseudo invalid instructions opcodes.
The disassember was generating invXXX instructions for cases when in reality we
had llockd or scondd instrutions.
opcodes/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
arc-tbl.h: Removed any "inv.+" instructions from the table.
gas/ChangeLog:
Cupertino Miranda <cmiranda@synopsys.com>
testsuite/arc/dis-inv.s: Test to validate patch.
testsuite/arc/dis-inv.d: Likewise.
Diffstat (limited to 'opcodes/arc-tbl.h')
| -rw-r--r-- | opcodes/arc-tbl.h | 93 |
1 files changed, 0 insertions, 93 deletions
diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h index 682b808..3246d8d 100644 --- a/opcodes/arc-tbl.h +++ b/opcodes/arc-tbl.h @@ -7766,99 +7766,6 @@ /* iaddr<.f><.cc> b,b,limm 00110bbb11100111FBBB1111100QQQQQ. */ { "iaddr", 0x30E70F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }}, -/* invld042e 00100RRRRR101110RRRRRRRRRRRRRRRR. */ -{ "invld042e", 0x202E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld042f0e 00100RRRRR101111RRRRRRRRRR00111R. */ -{ "invld042f0e", 0x202F000E, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld042f12 00100RRRRR101111RRRRRRRRRR01001R. */ -{ "invld042f12", 0x202F0012, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld042f14 00100RRRRR101111RRRRRRRRRR0101RR. */ -{ "invld042f14", 0x202F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld042f18 00100RRRRR101111RRRRRRRRRR011RRR. */ -{ "invld042f18", 0x202F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld042f20 00100RRRRR101111RRRRRRRRRR10RRRR. */ -{ "invld042f20", 0x202F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld042f30 00100RRRRR101111RRRRRRRRRR110RRR. */ -{ "invld042f30", 0x202F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld042f38 00100RRRRR101111RRRRRRRRRR1110RR. */ -{ "invld042f38", 0x202F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld042f3c 00100RRRRR101111RRRRRRRRRR11110R. */ -{ "invld042f3c", 0x202F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld042f3e 00100RRRRR101111RRRRRRRRRR111110. */ -{ "invld042f3e", 0x202F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld042f3f08 00100RRRRR101111R001RRRRRR111111. */ -{ "invld042f3f08", 0x202F103F, 0xF83F703F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld042f3f10 00100RRRRR101111R01RRRRRRR111111. */ -{ "invld042f3f10", 0x202F203F, 0xF83F603F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld042f3f20 00100RRRRR101111R1RRRRRRRR111111. */ -{ "invld042f3f20", 0x202F403F, 0xF83F403F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld0506 00101RRRRR00011RRRRRRRRRRRRRRRRR. */ -{ "invld0506", 0x28060000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld050a 00101RRRRR00101RRRRRRRRRRRRRRRRR. */ -{ "invld050a", 0x280A0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld050c 00101RRRRR00110RRRRRRRRRRRRRRRRR. */ -{ "invld050c", 0x280C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld051e 00101RRRRR01111RRRRRRRRRRRRRRRRR. */ -{ "invld051e", 0x281E0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld0520 00101RRRRR100RRRRRRRRRRRRRRRRRRR. */ -{ "invld0520", 0x28200000, 0xF8380000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld0528 00101RRRRR1010RRRRRRRRRRRRRRRRRR. */ -{ "invld0528", 0x28280000, 0xF83C0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld052c 00101RRRRR10110RRRRRRRRRRRRRRRRR. */ -{ "invld052c", 0x282C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld052e 00101RRRRR101110RRRRRRRRRRRRRRRR. */ -{ "invld052e", 0x282E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld052f02 00101RRRRR101111RRRRRRRRRR00001R. */ -{ "invld052f02", 0x282F0002, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld052f04 00101RRRRR101111RRRRRRRRRR0001RR. */ -{ "invld052f04", 0x282F0004, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld052f14 00101RRRRR101111RRRRRRRRRR0101RR. */ -{ "invld052f14", 0x282F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld052f18 00101RRRRR101111RRRRRRRRRR011RRR. */ -{ "invld052f18", 0x282F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld052f20 00101RRRRR101111RRRRRRRRRR10RRRR. */ -{ "invld052f20", 0x282F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld052f30 00101RRRRR101111RRRRRRRRRR110RRR. */ -{ "invld052f30", 0x282F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld052f38 00101RRRRR101111RRRRRRRRRR1110RR. */ -{ "invld052f38", 0x282F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld052f3c 00101RRRRR101111RRRRRRRRRR11110R. */ -{ "invld052f3c", 0x282F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld052f3e 00101RRRRR101111RRRRRRRRRR111110. */ -{ "invld052f3e", 0x282F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - -/* invld052f3f00 00101RRRRR101111RRRRRRRRRR111111. */ -{ "invld052f3f00", 0x282F003F, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }}, - /* j c 00100RRR001000000RRRCCCCCCRRRRRR. */ { "j", 0x20200000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }}, |