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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2016-04-06 16:08:04 +0200 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@synopsys.com> | 2016-04-12 10:21:06 +0200 |
| commit | f36e33dac1a97cca8f79ca8b20cf0fb05f1e25f4 (patch) | |
| tree | 36f13760bc5525172fce20159ffd3500e5ad17fd /opcodes/arc-opc.c | |
| parent | 1c2e355e4830814e18329a53d01cfa634d576211 (diff) | |
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Add support for .extCondCode, .extCoreRegister and .extAuxRegister.
gas/
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/textauxregister.d: New file.
* testsuite/gas/arc/textauxregister.s: Likewise.
* testsuite/gas/arc/textcondcode.d: Likewise.
* testsuite/gas/arc/textcondcode.s: Likewise.
* testsuite/gas/arc/textcoreregister.d: Likewise.
* testsuite/gas/arc/textcoreregister.s: Likewise.
* testsuite/gas/arc/textpseudoop.d: Likewise.
* testsuite/gas/arc/textpseudoop.s: Likewise.
* testsuite/gas/arc/ld2.d: Update test.
* testsuite/gas/arc/st.d: Likewise.
* testsuite/gas/arc/taux.d: Likewise.
* doc/c-arc.texi (ARC Directives): Add .extCondCode,
.extCoreRegister and .extAuxRegister documentation.
* config/tc-arc.c (arc_extcorereg): New function.
(md_pseudo_table): Add .extCondCode, .extCoreRegister and
.extAuxRegister pseudo-ops.
(extRegister_t): New type.
(ext_condcode, arc_aux_hash): New global variable.
(find_opcode_match): Check for extensions.
(preprocess_operands): Likewise.
(md_begin): Add aux registers in a hash.
(assemble_insn): Update use arc_flags member.
(tokenize_extregister): New function.
(create_extcore_section): Likewise.
* config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Increase to 10.
(arc_flags): Delete code, add flgp.
include/
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (flag_class_t): Update.
(ARC_OPCODE_NONE): Define.
(ARC_OPCODE_ARCALL): Likewise.
(ARC_OPCODE_ARCFPX): Likewise.
(ARC_REGISTER_READONLY): Likewise.
(ARC_REGISTER_WRITEONLY): Likewise.
(ARC_REGISTER_NOSHORT_CUT): Likewise.
(arc_aux_reg): Add cpu.
opcodes/
2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (find_format): Check for extension flags.
(print_flags): New function.
(print_insn_arc): Update for .extCondCode, .extCoreRegister and
.extAuxRegister.
* arc-ext.c (arcExtMap_coreRegName): Use
LAST_EXTENSION_CORE_REGISTER.
(arcExtMap_coreReadWrite): Likewise.
(dump_ARC_extmap): Update printing.
* arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
(arc_aux_regs): Add cpu field.
* arc-regs.h: Add cpu field, lower case name aux registers.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
Diffstat (limited to 'opcodes/arc-opc.c')
| -rw-r--r-- | opcodes/arc-opc.c | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c index 028b80b..5603ded 100644 --- a/opcodes/arc-opc.c +++ b/opcodes/arc-opc.c @@ -1048,12 +1048,13 @@ const struct arc_flag_class arc_flag_classes[] = { F_CLASS_NONE, { F_NULL } }, #define C_CC (C_EMPTY + 1) - { F_CLASS_OPTIONAL, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, - F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, - F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, - F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, - F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, - F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, + { F_CLASS_OPTIONAL | F_CLASS_EXTEND, + { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, + F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS, + F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR, + F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, + F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT, + F_LE, F_HI, F_LS, F_PNZ, F_NULL } }, #define C_AA_ADDR3 (C_CC + 1) #define C_AA27 (C_CC + 1) @@ -1729,8 +1730,8 @@ const unsigned arc_num_pseudo_insn = const struct arc_aux_reg arc_aux_regs[] = { #undef DEF -#define DEF(ADDR, SUBCLASS, NAME) \ - { ADDR, SUBCLASS, #NAME, sizeof (#NAME)-1 }, +#define DEF(ADDR, CPU, SUBCLASS, NAME) \ + { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 }, #include "arc-regs.h" |